[Qemu-devel] [PATCH qom-next v2 4/5] target-microblaze: Use parent class for reset + realize

[peter . crosthwaite]

From: Peter Crosthwaite <peter.crosthwa...@xilinx.com>

MicroblazeCPUClass is only needed for parent-class abstract function
access. Just use parent classes for reset and realize access and remove
MicroblazeCPUClass completely.

Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---

 target-microblaze/cpu-qom.h | 20 --------------------
 target-microblaze/cpu.c     | 16 ++++++----------
 2 files changed, 6 insertions(+), 30 deletions(-)

diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index 3e9c206..f47259b 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -24,28 +24,8 @@
 
 #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
 
-#define MICROBLAZE_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
 #define MICROBLAZE_CPU(obj) \
     OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU)
-#define MICROBLAZE_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU)
-
-/**
- * MicroBlazeCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- *
- * A MicroBlaze CPU model.
- */
-typedef struct MicroBlazeCPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-    void (*parent_reset)(CPUState *cpu);
-} MicroBlazeCPUClass;
 
 /**
  * MicroBlazeCPU:
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index a0fcdf4..e8d76b9 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -25,12 +25,12 @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 
-
 /* CPUClass::reset() */
 static void mb_cpu_reset(CPUState *s)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
-    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
+    CPUClass *cc_parent =
+            CPU_CLASS(object_class_get_parent_by_name(TYPE_MICROBLAZE_CPU));
     CPUMBState *env = &cpu->env;
 
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
@@ -38,7 +38,7 @@ static void mb_cpu_reset(CPUState *s)
         log_cpu_state(env, 0);
     }
 
-    mcc->parent_reset(s);
+    cc_parent->reset(s);
 
     memset(env, 0, offsetof(CPUMBState, breakpoints));
     env->res_addr = RES_ADDR_NONE;
@@ -89,11 +89,11 @@ static void mb_cpu_reset(CPUState *s)
 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
-    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
-
+    DeviceClass *dc_parent =
+            DEVICE_CLASS(object_class_get_parent_by_name(TYPE_MICROBLAZE_CPU));
     cpu_reset(CPU(cpu));
 
-    mcc->parent_realize(dev, errp);
+    dc_parent->realize(dev, errp);
 }
 
 static void mb_cpu_initfn(Object *obj)
@@ -128,12 +128,9 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
-    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 
-    mcc->parent_realize = dc->realize;
     dc->realize = mb_cpu_realizefn;
 
-    mcc->parent_reset = cc->reset;
     cc->reset = mb_cpu_reset;
 
     cc->do_interrupt = mb_cpu_do_interrupt;
@@ -148,7 +145,6 @@ static const TypeInfo mb_cpu_type_info = {
     .parent = TYPE_CPU,
     .instance_size = sizeof(MicroBlazeCPU),
     .instance_init = mb_cpu_initfn,
-    .class_size = sizeof(MicroBlazeCPUClass),
     .class_init = mb_cpu_class_init,
 };
 
-- 
1.8.3.rc1.44.gb387c77.dirty