[Qemu-devel] [PATCH qom-cpu 3/3] target-i386: Change do_smm_enter() argument to X86CPU

[Andreas Färber]

log_cpu_state_mask() needs CPUState.

Signed-off-by: Andreas Färber <afaer...@suse.de>
---
 cpu-exec.c               | 2 +-
 target-i386/cpu.h        | 2 +-
 target-i386/smm_helper.c | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu-exec.c b/cpu-exec.c
index 9c46846..6c784a7 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -331,7 +331,7 @@ int cpu_exec(CPUArchState *env)
                             cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
                                                           0);
                             cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
-                            do_smm_enter(env);
+                            do_smm_enter(x86_env_get_cpu(env));
                             next_tb = 0;
                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
                                    !(env->hflags2 & HF2_NMI_MASK)) {
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 2849672..2d005b3 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1220,7 +1220,7 @@ void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, 
uint64_t exit_info_1);
 /* seg_helper.c */
 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
 
-void do_smm_enter(CPUX86State *env1);
+void do_smm_enter(X86CPU *cpu);
 
 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
 
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 5abdfc8..6cb4551 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -24,7 +24,7 @@
 
 #if defined(CONFIG_USER_ONLY)
 
-void do_smm_enter(CPUX86State *env)
+void do_smm_enter(X86CPU *cpu)
 {
 }
 
@@ -40,9 +40,9 @@ void helper_rsm(CPUX86State *env)
 #define SMM_REVISION_ID 0x00020000
 #endif
 
-void do_smm_enter(CPUX86State *env)
+void do_smm_enter(X86CPU *cpu)
 {
-    X86CPU *cpu = x86_env_get_cpu(env);
+    CPUX86State *env = &cpu->env;
     target_ulong sm_state;
     SegmentCache *dt;
     int i, offset;
-- 
1.8.1.4