On Tue, Jun 11, 2013 at 10:56:55AM +1000, peter.crosthwa...@xilinx.com wrote: > From: Peter Crosthwaite <peter.crosthwa...@xilinx.com> > > > Various fixups to the Xilinx Interrupt controller following a review > against TRM and RTL descriptions. > > Tested as working for microblaze and microblazeel Linux. > > change from v1: > Fixed S3ADSP UART interrupt - done first for bisectability > (Now tested as working on s3asdsp design)
Applied, thanks Peter. Cheers, Edgar > > > Peter Crosthwaite (5): > microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ > intc/xilinx_intc: Don't clear level sens. IRQs without ACK > intc/xilinx_intc: Handle level interrupt retriggering > intc/xilinx_intc: Inhibit write to ISR when HIE > intc/xilinx_intc: Dont lower IRQ when HIE cleared > > hw/intc/xilinx_intc.c | 28 ++++++++++++++++++---------- > hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- > 2 files changed, 19 insertions(+), 11 deletions(-) > > -- > 1.8.3.rc1.44.gb387c77.dirty >
