On 27 May 2013 09:19, Paolo Bonzini <pbonz...@redhat.com> wrote: > Il 27/05/2013 09:23, Jan Kiszka ha scritto: >> Err, why? Will we emulate IOMMUs for TCG differently? > > Because IOMMUs should never be added to address_space_memory. > > TCG should only encounter an IOMMU during device emulation (DMA), not > because of reads/writes from the CPU. So the IOTLBs should never point > to an IOMMU region.
This seems a slightly dubious assumption to me. For instance here's a sample system diagram that puts a Cortex-M3 CPU behind an IOMMU (the MMU-500 dotted line): http://www.arm.com/images/CoreLink_MMU-500_in_System.jpg Admittedly we're a long way from being able to model that since we don't support multiple CPUs in one system yet. Can we have an assertion if you try to add an IOMMU to the CPU's view of memory, so it's obvious if we ever do run into this case? thanks -- PMM
