> On 2013-05-07 19:26, Jan Kiszka wrote: > > Well, the alternative is to handle a sub-page dispatch (ie. calling into > > subpage_[ram_]read/write just like address_space_rw: take the necessary > > lock that protect mapping changes, look into the sub-page and pick up > > the target region, invoke memory_region_ref on it, perform the access > > and unref the region again. Slow, but that's how sub-pages are. And it > > only affects TCG. Hmm, or does your IOMMU core cache translations on a > > per-page base as well? > > OK, there is no translation caching in the memory core. So I will > preserve the dispatching functions of sub-pages, just like the term > "sub-page" - along with a comment why we depend on page granularity.
Note that TCG will cache translations because the TLB entry is filled with the page after translation has taken place. In fact, this is the main change from Avi's series to mine, and a side-effect of centralizing the translation in address_space_translate. It shouldn't be a problem though, the TLB entry will point to the subpage and the compiled code will dispatch to it. Paolo
