On Oct 22, 2009, at 11:39, ext Laurent Desnogues wrote:
> On Wed, Oct 21, 2009 at 12:17 PM, <juha.riihim...@nokia.com> wrote:
>> Add support for neon vld1.64 instruction.
>>
>> From: Riku Voipio <riku.voi...@iki.fi>
>> Signed-off-by: Juha Riihimäki <juha.riihim...@nokia.com>
>> ---
>> diff --git a/target-arm/translate.c b/target-arm/translate.c
>> index 3ea9d51..d027572 100644
>> --- a/target-arm/translate.c
>> +++ b/target-arm/translate.c
>> @@ -795,6 +795,12 @@ static inline TCGv gen_ld32(TCGv addr, int
>> index)
>> tcg_gen_qemu_ld32u(tmp, addr, index);
>> return tmp;
>> }
>> +static inline TCGv_i64 gen_ld64(TCGv addr, int index)
>> +{
>> + TCGv_i64 tmp = tcg_temp_new_i64();
>> + tcg_gen_qemu_ld64(tmp, addr, index);
>> + return tmp;
>> +}
>> static inline void gen_st8(TCGv val, TCGv addr, int index)
>> {
>> tcg_gen_qemu_st8(val, addr, index);
>> @@ -810,6 +816,11 @@ static inline void gen_st32(TCGv val, TCGv addr,
>> int index)
>> tcg_gen_qemu_st32(val, addr, index);
>> dead_tmp(val);
>> }
>> +static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
>> +{
>> + tcg_gen_qemu_st64(val, addr, index);
>> + tcg_temp_free_i64(val);
>> +}
>>
>> static inline void gen_set_pc_im(uint32_t val)
>> {
>> @@ -3690,6 +3701,7 @@ static int disas_neon_ls_insn(CPUState * env,
>> DisasContext *s, uint32_t insn)
>> TCGv addr;
>> TCGv tmp;
>> TCGv tmp2;
>> + TCGv_i64 tmp64;
>>
>> if (!vfp_enabled(env))
>> return 1;
>> @@ -3702,7 +3714,7 @@ static int disas_neon_ls_insn(CPUState * env,
>> DisasContext *s, uint32_t insn)
>> /* Load store all elements. */
>> op = (insn >> 8) & 0xf;
>> size = (insn >> 6) & 3;
>> - if (op > 10 || size == 3)
>> + if (op > 10)
>
> This is wrong: a size of 3 is limited to vld1.64 and vst1.64 which
> you don't enforce here.
>
> Apart from that, the rest looks OK.
Thanks, and you're right of course. I'll add a check that will return
1 if size equals 3 and interleave or spacing is not 1.
Cheers,
Juha
