On 26.04.2013, at 11:38, Aurelien Jarno wrote:
> On Fri, Apr 26, 2013 at 09:50:31AM +0200, Alexander Graf wrote:
>>
>> On 20.04.2013, at 20:56, Aurelien Jarno wrote:
>>
>>> Needed for Power ISA version 2.05 compliance.
>>>
>>> Reviewed-by: Richard Henderson <r...@twiddle.net>
>>> Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
>>> ---
>>> target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 38 insertions(+)
>>>
>>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>>> index 6bee6db..977f9ef 100644
>>> --- a/target-ppc/translate.c
>>> +++ b/target-ppc/translate.c
>>> @@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
>>> }
>>> #endif
>>>
>>> +/* prtyw: PowerPC 2.05 specification */
>>> +static void gen_prtyw(DisasContext *ctx)
>>> +{
>>> + TCGv ra = cpu_gpr[rA(ctx->opcode)];
>>> + TCGv rs = cpu_gpr[rS(ctx->opcode)];
>>> + TCGv t0 = tcg_temp_new();
>>> + tcg_gen_shri_tl(t0, rs, 16);
>>> + tcg_gen_xor_tl(ra, rs, t0);
>>> + tcg_gen_shri_tl(t0, ra, 8);
>>> + tcg_gen_xor_tl(ra, ra, t0);
>>> +#if defined(TARGET_PPC64)
>>> + tcg_gen_andi_tl(ra, ra, 0x100000001);
>>
>> This will break on 32-bit host systems. Let me fix it to ULL for you :). In
>> fact, any reason for the #ifdef here? We could just always pass
>> 0x100000001ULL and have the target_ulong cast take the upper 32bit away, no?
>
> Good catch. The #ifdef version matches the instruction definition in the
> manual, but for QEMU I agree a version using a cast with target_ulong
> looks better. Should I send a new patch?
I already fixed it up while applying the patch, thanks :)
Alex
