On Thu, Apr 04, 2013 at 05:55:53PM -0500, Richard Henderson wrote: > Changes v3-v4: > > There were two problems, both related to the setcond opcode: > > * The first was pre-existing: the current code gets 32-bit NE wrong, > failing to ignore the high 32-bits of the register. This problem > caused the rest of the patch set to be non-bisectable -- any non- > trivial change to code generation of the 32-bit opcodes tended to > expose this. > > * The second was in the setcond rewrite, in that my logic was wrong > for the signed comparisons. > > In the process of tracking all of this down, I split up the setcond > changes into three parts, and dropped the carry-bit optimization part > entirely. It may still be an improvement for the unsigned comparisons, > but since I have switched to MFOCRF it'll be harder to show a speedup > in practice. > > Finally, one extra patch to avoid a regression in code generation when > insertting zero via deposit. > > Tested with arm-test, sparc-test, and i386-softmmu nbench. > > Tree updated at > > git://github.com/rth7680/qemu.git tcg-ppc64 >
Oops it looks like I reviewed the V3, while testing the version in your git tree, so the V4. Therefore my comments about the tests I have done apply to this version, and I'll review the remaining patches of this version over the week-end. Tested-by: Aurelien Jarno <aurel...@aurel32.net> -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurel...@aurel32.net http://www.aurel32.net
