Hi Kuo-Jung,
On Wed, Feb 27, 2013 at 5:15 PM, Kuo-Jung Su <dant...@gmail.com> wrote:
> From: Kuo-Jung Su <dant...@faraday-tech.com>
>
> It's used to perform AHB remap and if the SDRAM is initialized
> before AHB remap process activated, then it would also perform
> the QEMU RAM initialization.
>
> Signed-off-by: Kuo-Jung Su <dant...@faraday-tech.com>
> ---
> hw/arm/Makefile.objs | 1 +
> hw/arm/faraday_a369_soc.c | 3 +
> hw/arm/ftahbc020.c | 189
> +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 193 insertions(+)
> create mode 100644 hw/arm/ftahbc020.c
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 6771072..33c9482 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -38,3 +38,4 @@ obj-y += faraday_a369.o \
> faraday_a369_scu.o \
> faraday_a369_kpd.o
> obj-y += ftintc020.o
> +obj-y += ftahbc020.o
> diff --git a/hw/arm/faraday_a369_soc.c b/hw/arm/faraday_a369_soc.c
> index 3d861d2..e7343d9 100644
> --- a/hw/arm/faraday_a369_soc.c
> +++ b/hw/arm/faraday_a369_soc.c
> @@ -145,6 +145,9 @@ a369soc_device_init(FaradaySoCState *s)
>
> /* ftkbc010 */
> sysbus_create_simple("a369.keypad", 0x92f00000, pic[21]);
> +
> + /* ftahbc020 */
> + s->ahbc = sysbus_create_simple("ftahbc020", 0x94000000, NULL);
> }
>
> static int a369soc_init(SysBusDevice *busdev)
> diff --git a/hw/arm/ftahbc020.c b/hw/arm/ftahbc020.c
> new file mode 100644
> index 0000000..b558e90
> --- /dev/null
> +++ b/hw/arm/ftahbc020.c
> @@ -0,0 +1,189 @@
> +/*
> + * Faraday AHB controller
> + *
> + * Copyright (c) 2012 Faraday Technology
> + * Written by Dante Su <dant...@faraday-tech.com>
> + *
> + * This code is licensed under GNU GPL v2+
> + */
> +
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/devices.h"
> +#include "sysemu/sysemu.h"
> +
> +#include "faraday.h"
> +
> +#define REG_SLAVE(n) ((n) * 4) /* Slave config (base & size) */
> +#define REG_PRIR 0x80 /* Priority register */
> +#define REG_IDLECR 0x84 /* IDLE count register */
> +#define REG_CR 0x88 /* Control register */
> +#define REG_REVR 0x8c /* Revision register */
> +
> +#define CR_REMAP 0x01 /* Enable AHB remap for slave 4 & 6 */
> +
> +#define TYPE_FTAHBC020 "ftahbc020"
> +
> +typedef struct Ftahbc020State {
> + SysBusDevice busdev;
> + MemoryRegion iomem;
> +
> + /* HW register cache */
> + uint32_t cr;
> +} Ftahbc020State;
> +
> +#define FTAHBC020(obj) \
> + OBJECT_CHECK(Ftahbc020State, obj, TYPE_FTAHBC020)
> +
> +static uint64_t
> +ftahbc020_mem_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + Ftahbc020State *s = FTAHBC020(opaque);
> + FaradaySoCState *soc = FARADAY_SOC_GET_CORE();
> + uint64_t ret = 0;
> +
> + switch (addr) {
> + /* slave address & window configuration */
> + case REG_SLAVE(0) ... REG_SLAVE(3):
> + case REG_SLAVE(5):
I think its required to have a comment of fall through case statements.
/* fall-through - because of foo */
Regards,
Peter
> + case REG_SLAVE(7) ... REG_SLAVE(31):
> + ret = soc->ahb_slave[addr / 4];
> + break;
> + case REG_SLAVE(4):
> + ret = soc->rom_base | (soc->ahb_slave[4] & 0x000f0000);
> + break;
> + case REG_SLAVE(6):
> + ret = soc->ram_base | (soc->ahb_slave[6] & 0x000f0000);
> + break;
> + /* control register */
> + case REG_CR:
> + if (soc->ahb_remapped) {
> + s->cr |= CR_REMAP;
> + }
> + ret = s->cr;
> + break;
> + case REG_REVR:
> + ret = 0x00010301; /* rev. 1.3.1 */
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "ftahbc020: undefined memory access@0x%llx\n", addr);
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void
> +ftahbc020_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> +{
> + Ftahbc020State *s = FTAHBC020(opaque);
> + FaradaySoCState *soc = FARADAY_SOC_GET_CORE();
> +
> + switch (addr) {
> + case REG_CR: /* control register */
> + s->cr = (uint32_t)val;
> + if (soc->ahb_remapped && !(s->cr & CR_REMAP)) {
> + hw_error("ftahbc020: Once AHB remap is enabled, "
> + "it could not be disabled!\n");
> + exit(1);
> + }
> + if (!soc->ahb_remapped && (s->cr & CR_REMAP)) {
> + /* Remap AHB slave 4 (ROM) & slave 6 (RAM) */
> + /* 1. Remap RAM to base of ROM */
> + soc->ram_base = soc->ahb_slave[4] & 0xfff00000;
> + /* 2. Remap ROM to base of ROM + size of RAM */
> + soc->rom_base = soc->ram_base
> + + ((1 << extract32(soc->ahb_slave[6], 16, 4)) <<
> 20);
> + /* 3. Update ROM memory map */
> + sysbus_mmio_map(SYS_BUS_DEVICE(soc->rom), 0, soc->rom_base);
> + /* 4. Update RAM memory map if it has been initialized. */
> + if (soc->ddr_inited) {
> + memory_region_del_subregion(soc->as, soc->ram);
> + memory_region_add_subregion(soc->as, soc->ram_base,
> soc->ram);
> + }
> + soc->ahb_remapped = true;
> + }
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "ftahbc020: undefined memory access@0x%llx\n", addr);
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps mmio_ops = {
> + .read = ftahbc020_mem_read,
> + .write = ftahbc020_mem_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> +static void ftahbc020_reset(DeviceState *ds)
> +{
> + SysBusDevice *busdev = SYS_BUS_DEVICE(ds);
> + Ftahbc020State *s = FTAHBC020(FROM_SYSBUS(Ftahbc020State, busdev));
> + FaradaySoCState *soc = FARADAY_SOC_GET_CORE();
> +
> + if (soc->ahb_remapped && !soc->bi) {
> + soc->rom_base = soc->ahb_slave[4] & 0xfff00000;
> + soc->ram_base = soc->ahb_slave[6] & 0xfff00000;
> + sysbus_mmio_map(SYS_BUS_DEVICE(soc->rom), 0, soc->rom_base);
> + soc->ahb_remapped = false;
> + }
> +
> + s->cr = 0;
> +}
> +
> +static int ftahbc020_init(SysBusDevice *dev)
> +{
> + Ftahbc020State *s = FTAHBC020(FROM_SYSBUS(Ftahbc020State, dev));
> +
> + memory_region_init_io(&s->iomem,
> + &mmio_ops,
> + s,
> + TYPE_FTAHBC020,
> + 0x1000);
> + sysbus_init_mmio(dev, &s->iomem);
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_ftahbc020 = {
> + .name = TYPE_FTAHBC020,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(cr, Ftahbc020State),
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static void ftahbc020_class_init(ObjectClass *klass, void *data)
> +{
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + k->init = ftahbc020_init;
> + dc->desc = TYPE_FTAHBC020;
> + dc->vmsd = &vmstate_ftahbc020;
> + dc->reset = ftahbc020_reset;
> + dc->no_user = 1;
> +}
> +
> +static const TypeInfo ftahbc020_info = {
> + .name = TYPE_FTAHBC020,
> + .parent = TYPE_FARADAY_SOC,
> + .instance_size = sizeof(Ftahbc020State),
> + .class_init = ftahbc020_class_init,
> +};
> +
> +static void ftahbc020_register_types(void)
> +{
> + type_register_static(&ftahbc020_info);
> +}
> +
> +type_init(ftahbc020_register_types)
> --
> 1.7.9.5
>
>
