It broke mingw build with gcc-3.4.2 gcc -Wall -O2 -g -fno-strict-aliasing -fno-reorder-blocks -fno-gcse -fno-optimize-sibling-calls -fno-crossjumping -fno-align-labels -fno-align-jumps -fno-align-functions -mpreferred-stack-boundary=2 -fomit-frame-pointer -I. -I.. -I/c/qemu/target-i386 -I/c/qemu -MMD -MP -DNEED_CPU_H -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -I/c/qemu/fpu -DHAS_AUDIO -DHAS_AUDIO_CHOICE -I/c/qemu/slirp -c -o op.o /c/qemu/target-i386/op.c c:/qemu/target-i386/ops_mem.h: In function `op_stw_kernel_T1_A0': ../softmmu_header.h:174: error: can't find a register in class `Q_REGS' while reloading `asm' make[1]: *** [op.o] Error 1 make[1]: Leaving directory `/c/qemu/i386-softmmu' make: *** [subdir-i386-softmmu] Error 2
Alex. "Alexander Graf" <[EMAIL PROTECTED]> wrote in message news:[EMAIL PROTECTED] > Johannes Schindelin wrote: >> Hi, >> >> On Thu, 17 Jan 2008, Johannes Schindelin wrote: >> >> >>> It fixed it for me, but only after a "make distclean && ./configure && >>> make". Apparently there are still some dependencies which are not >>> right. >>> >> >> Spoke too soon... It introduces an extra #endif in target-mips/exec.h >> >> > > Right, thanks. > > New patch attached. > > Alex > -------------------------------------------------------------------------------- > Index: qemu/softmmu_header.h > =================================================================== > --- qemu.orig/softmmu_header.h > +++ qemu/softmmu_header.h > @@ -189,9 +189,15 @@ static inline void glue(glue(st, SUFFIX) > #else > #error unsupported size > #endif > +#ifdef GCC_BREAKS_T_REGISTER > + "pushl %%ecx\n" > +#endif > "pushl %6\n" > "call %7\n" > "popl %%eax\n" > +#ifdef GCC_BREAKS_T_REGISTER > + "popl %%ecx\n" > +#endif > "jmp 2f\n" > "1:\n" > "addl 8(%%edx), %%eax\n" > @@ -209,14 +215,22 @@ static inline void glue(glue(st, SUFFIX) > : "r" (ptr), > /* NOTE: 'q' would be needed as constraint, but we could not use it > with T1 ! */ > +#if DATA_SIZE == 1 || DATA_SIZE == 2 > + "q" (v), > +#else > "r" (v), > +#endif > "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), > "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), > "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), > "m" (*(uint32_t *)offsetof(CPUState, > tlb_table[CPU_MMU_INDEX][0].addr_write)), > "i" (CPU_MMU_INDEX), > "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX)) > +#ifdef GCC_BREAKS_T_REGISTER > + : "%eax", "%edx", "memory", "cc"); > +#else > : "%eax", "%ecx", "%edx", "memory", "cc"); > +#endif > } > > #else > Index: qemu/target-alpha/cpu.h > =================================================================== > --- qemu.orig/target-alpha/cpu.h > +++ qemu/target-alpha/cpu.h > @@ -275,6 +275,8 @@ struct CPUAlphaState { > * used to emulate 64 bits target on 32 bits hosts > */ > target_ulong t0, t1, t2; > +#elif defined(GCC_BREAKS_T_REGISTER) > + target_ulong t2; > #endif > /* */ > double ft0, ft1, ft2; > Index: qemu/target-alpha/exec.h > =================================================================== > --- qemu.orig/target-alpha/exec.h > +++ qemu/target-alpha/exec.h > @@ -36,6 +36,12 @@ register struct CPUAlphaState *env asm(A > #define T1 (env->t1) > #define T2 (env->t2) > > +#elif defined(GCC_BREAKS_T_REGISTER) > + > +register uint64_t T0 asm(AREG1); > +register uint64_t T1 asm(AREG2); > +#define T2 (env->t2) > + > #else > > register uint64_t T0 asm(AREG1); > Index: qemu/target-arm/cpu.h > =================================================================== > --- qemu.orig/target-arm/cpu.h > +++ qemu/target-arm/cpu.h > @@ -66,6 +66,9 @@ typedef uint32_t ARMReadCPFunc(void *opa > */ > > typedef struct CPUARMState { > +#if defined(GCC_BREAKS_T_REGISTER) > + uint32_t t2; > +#endif > /* Regs for current mode. */ > uint32_t regs[16]; > /* Frequently accessed CPSR bits are stored separately for > efficiently. > Index: qemu/target-arm/exec.h > =================================================================== > --- qemu.orig/target-arm/exec.h > +++ qemu/target-arm/exec.h > @@ -23,7 +23,12 @@ > register struct CPUARMState *env asm(AREG0); > register uint32_t T0 asm(AREG1); > register uint32_t T1 asm(AREG2); > +#if defined(GCC_BREAKS_T_REGISTER) > +#define T2 (env->t2) > +#else > register uint32_t T2 asm(AREG3); > +#endif > + > > /* TODO: Put these in FP regs on targets that have such things. */ > /* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */ > Index: qemu/target-i386/cpu.h > =================================================================== > --- qemu.orig/target-i386/cpu.h > +++ qemu/target-i386/cpu.h > @@ -470,6 +470,8 @@ typedef struct CPUX86State { > #if TARGET_LONG_BITS > HOST_LONG_BITS > /* temporaries if we cannot store them in host registers */ > target_ulong t0, t1, t2; > +#elif defined(GCC_BREAKS_T_REGISTER) > + target_ulong t1; > #endif > > /* standard registers */ > Index: qemu/target-i386/exec.h > =================================================================== > --- qemu.orig/target-i386/exec.h > +++ qemu/target-i386/exec.h > @@ -39,6 +39,12 @@ register struct CPUX86State *env asm(ARE > #define T1 (env->t1) > #define T2 (env->t2) > > +#elif defined(GCC_BREAKS_T_REGISTER) > + > +register target_ulong T0 asm(AREG1); > +#define T1 (env->t1) > +register target_ulong T2 asm(AREG3); > + > #else > > /* XXX: use unsigned long instead of target_ulong - better code will > Index: qemu/target-mips/cpu.h > =================================================================== > --- qemu.orig/target-mips/cpu.h > +++ qemu/target-mips/cpu.h > @@ -149,6 +149,8 @@ struct CPUMIPSState { > target_ulong t0; > target_ulong t1; > target_ulong t2; > +#elif defined(GCC_BREAKS_T_REGISTER) > + target_ulong t2; > #endif > target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX]; > target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX]; > Index: qemu/target-mips/exec.h > =================================================================== > --- qemu.orig/target-mips/exec.h > +++ qemu/target-mips/exec.h > @@ -14,6 +14,10 @@ register struct CPUMIPSState *env asm(AR > #define T0 (env->t0) > #define T1 (env->t1) > #define T2 (env->t2) > +#elif defined(GCC_BREAKS_T_REGISTER) > +register target_ulong T0 asm(AREG1); > +register target_ulong T1 asm(AREG2); > +#define T2 (env->t2) > #else > register target_ulong T0 asm(AREG1); > register target_ulong T1 asm(AREG2); > Index: qemu/target-ppc/exec.h > =================================================================== > --- qemu.orig/target-ppc/exec.h > +++ qemu/target-ppc/exec.h > @@ -38,10 +38,15 @@ register struct CPUPPCState *env asm(ARE > #define T1 (env->t1) > #define T2 (env->t2) > #define TDX "%016" PRIx64 > +#elif defined(GCC_BREAKS_T_REGISTER) > +register unsigned long T0 asm(AREG1); > +register unsigned long T1 asm(AREG2); > +#define T2 (env->t2) > #else > register unsigned long T0 asm(AREG1); > register unsigned long T1 asm(AREG2); > register unsigned long T2 asm(AREG3); > +#endif > #define TDX "%016lx" > #endif > /* We may, sometime, need 64 bits registers on 32 bits targets */ > Index: qemu/target-sparc/exec.h > =================================================================== > --- qemu.orig/target-sparc/exec.h > +++ qemu/target-sparc/exec.h > @@ -32,9 +32,13 @@ register uint32_t T2 asm(AREG4); > > #else > #define REGWPTR env->regwptr > +#if !defined(GCC_BREAKS_T_REGISTER) > register uint32_t T2 asm(AREG3); > -#endif > #define reg_T2 > +#else > +#define T2 (env->t2) > +#endif > +#endif > #endif > > #define FT0 (env->ft0) > Index: qemu/configure > =================================================================== > --- qemu.orig/configure > +++ qemu/configure > @@ -806,6 +806,12 @@ echo "AIOLIBS=$AIOLIBS" >> $config_mak > if test "$cpu" = "i386" ; then > echo "ARCH=i386" >> $config_mak > echo "#define HOST_I386 1" >> $config_h > + > + # add check for gcc4 breakage > + echo "#if (__GNUC__ > 3)" >> $config_h > + echo "#define GCC_BREAKS_T_REGISTER" >> $config_h > + echo "#endif" >> $config_h > + > elif test "$cpu" = "x86_64" ; then > echo "ARCH=x86_64" >> $config_mak > echo "#define HOST_X86_64 1" >> $config_h >
