[Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond

[Richard Henderson]

Signed-off-by: Richard Henderson <r...@twiddle.net>
---
 target-i386/translate.c | 52 ++++++++++++++++++++++++++-----------------------
 1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 2a220c1..9752c16 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2410,33 +2410,37 @@ static inline void gen_jcc(DisasContext *s, int b,
 static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b,
                         int modrm, int reg)
 {
-    int l1, mod = (modrm >> 6) & 3;
-    TCGv t0 = tcg_temp_local_new();
+    CCPrepare cc;
 
-    if (mod != 3) {
-        int reg_addr, offset_addr;
-        gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
-        gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
-    } else {
-        int rm = (modrm & 7) | REX_B(s);
-        gen_op_mov_v_reg(ot, t0, rm);
-    }
+    gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
 
-    l1 = gen_new_label();
-    gen_jcc1(s, b ^ 1, l1);
-#ifdef TARGET_X86_64
-    if (ot == OT_LONG) {
-        tcg_gen_mov_tl(cpu_regs[reg], t0);
-        gen_set_label(l1);
-        tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
-    } else
-#endif
-    {
-        gen_op_mov_reg_v(ot, reg, t0);
-        gen_set_label(l1);
-    }
+    cc = gen_prepare_cc(s, b, cpu_T[1]);
+    switch (cc.cond) {
+    default:
+        if (cc.mask != -1) {
+            TCGv t0 = tcg_temp_new();
+            tcg_gen_andi_tl(t0, cc.reg, cc.mask);
+            cc.reg = t0;
+        }
+        if (!cc.use_reg2) {
+            cc.reg2 = tcg_const_tl(cc.imm);
+        }
 
-    tcg_temp_free(t0);
+        tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
+                           cpu_T[0], cpu_regs[reg]);
+
+        if (cc.mask != -1) {
+            tcg_temp_free(cc.reg);
+        }
+        if (!cc.use_reg2) {
+            tcg_temp_free(cc.reg2);
+        }
+        /* FALLTHRU */
+    case TCG_COND_ALWAYS:
+        gen_op_mov_reg_T0(ot, reg);
+    case TCG_COND_NEVER:
+        break;
+    }
 }
 
 static inline void gen_op_movl_T0_seg(int seg_reg)
-- 
1.7.11.7