Several ACPI entries were missing from the bios and the new controllers
need to be initialized properly.
Furthermore COM2 is not being emulated, so Mac OS X broke trying to
initialize it.
The HPET ACPI table parts are optional.
This patch is against the bochsbios. Should this rather be sent to the
bochs ML?
Index: acpi-dsdt.dsl
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/acpi-dsdt.dsl,v
retrieving revision 1.1
diff -u -r1.1 acpi-dsdt.dsl
--- acpi-dsdt.dsl 28 Sep 2006 18:56:20 -0000 1.1
+++ acpi-dsdt.dsl 8 Jan 2008 14:05:34 -0000
@@ -25,6 +25,93 @@
0x1 // OEM Revision
)
{
+ OperationRegion (GNVS, SystemMemory, 0x7EEDBC10, 0x0100)
+ Field (GNVS, AnyAcc, Lock, Preserve)
+ {
+ OSYS, 16,
+ SMIF, 8,
+ PRM0, 8,
+ PRM1, 8,
+ SCIF, 8,
+ PRM2, 8,
+ PRM3, 8,
+ LCKF, 8,
+ PRM4, 8,
+ PRM5, 8,
+ P80D, 32,
+ LIDS, 8,
+ PWRS, 8,
+ DBGS, 8,
+ Offset (0x14),
+ ACTT, 8,
+ PSVT, 8,
+ TC1V, 8,
+ TC2V, 8,
+ TSPV, 8,
+ CRTT, 8,
+ DTSE, 8,
+ DTS1, 8,
+ DTS2, 8,
+ DTSF, 8,
+ BNUM, 8,
+ B0SC, 8,
+ B1SC, 8,
+ B2SC, 8,
+ B0SS, 8,
+ B1SS, 8,
+ B2SS, 8,
+ Offset (0x28),
+ APIC, 8,
+ MPEN, 8,
+ PPCS, 8,
+ PPCM, 8,
+ Offset (0x32),
+ NATP, 8,
+ CMAP, 8,
+ CMBP, 8,
+ LPTP, 8,
+ FDCP, 8,
+ CMCP, 8,
+ CIRP, 8,
+ Offset (0x3C),
+ IGDS, 8,
+ TLST, 8,
+ CADL, 8,
+ PADL, 8,
+ CSTE, 16,
+ NSTE, 16,
+ SSTE, 16,
+ NDID, 8,
+ DID1, 32,
+ DID2, 32,
+ DID3, 32,
+ DID4, 32,
+ DID5, 32,
+ BDSP, 8,
+ PTY1, 8,
+ PTY2, 8,
+ PSCL, 8,
+ TVF1, 8,
+ TVF2, 8,
+ Offset (0x67),
+ BLCS, 8,
+ BRTL, 8,
+ ALSE, 8,
+ ALAF, 8,
+ LLOW, 8,
+ LHIH, 8,
+ Offset (0x6E),
+ EMAE, 8,
+ EMAP, 16,
+ EMAL, 16,
+ Offset (0x74),
+ MEFE, 8,
+ Offset (0x82),
+ GTF0, 56,
+ GTF2, 56,
+ IDEM, 8
+ }
+
Scope (\)
{
/* CMOS memory access */
@@ -47,11 +134,114 @@
{
DBGL, 32,
}
+
+ /* PIC mode setting */
+ Name (PICF, 0x00)
+ Method (_PIC, 1, NotSerialized)
+ {
+ Store(Arg0, PICF)
+ }
+ Name (SSDT, Package (0x0C)
+ {
+ "CPU0IST ",
+ 0x7EEB8C10,
+ 0x0000026C,
+ "CPU1IST ",
+ 0x7EEB8F10,
+ 0x00000087,
+ "CPU0CST ",
+ 0x7EEB8910,
+ 0x000002A0,
+ "CPU1CST ",
+ 0x7EEB7F10,
+ 0x00000085
+ })
+ Name (CFGD, 0x011B49B1)
+ Name (\PDC0, 0x80000000)
+ Name (\PDC1, 0x80000000)
+ Name (\SDTL, 0x00)
}
+ Scope (\_PR)
+ {
+ Processor (CPU0, 0x00, 0x00000680, 0x06) {}
+ /* Processor (CPU1, 0x01, 0x00000410, 0x06) {} */
+ }
/* PCI Bus definition */
Scope(\_SB) {
+ OperationRegion (XXX, SystemIO, 0x300, 0x01)
+ Method (_INI, 0, NotSerialized)
+ {
+ Store (0x1, XXX)
+ If (CondRefOf (_OSI, Local0))
+ {
+ If (_OSI ("Darwin"))
+ {
+ Store (0x2710, OSYS)
+ }
+ }
+
+ Store (0x35, SMIF)
+ }
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_CID, 0x010CD041)
+ Name (BUF0, ResourceTemplate ()
+ {
+ IRQNoFlags ()
+ {0}
+ IRQNoFlags ()
+ {8}
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ _Y16)
+ })
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+
+ Return (BUF0)
+ }
+ }
+
+ Device (SMC)
+ {
+ Name (_HID, EisaId ("APP0001"))
+ Name (_CID, "smc-napa")
+ Name (_STA, 0x0B)
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0300, // Range Minimum
+ 0x0300, // Range Maximum
+ 0x01, // Alignment
+ 0x20, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ })
+ }
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ })
+ }
+
Device(PCI0) {
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
@@ -300,6 +492,7 @@
}
}
+/*
Device (COM2)
{
Name (_HID, EisaId ("PNP0501"))
@@ -327,6 +520,7 @@
Return (BUF0)
}
}
+*/
}
/* PIIX4 PM */
Index: rombios.c
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
retrieving revision 1.176
diff -u -r1.176 rombios.c
--- rombios.c 30 Dec 2006 17:13:17 -0000 1.176
+++ rombios.c 8 Jan 2008 14:05:52 -0000
@@ -9513,6 +9513,14 @@
mov eax, #0x00040000
call eax
+ ;; reset the memory (some boot loaders such as syslinux suppose
+ ;; that the memory is set to zero)
+ mov edi, #0x00040000
+ mov ecx, #0x40000 / 4
+ xor eax, eax
+ rep
+ stosd
+
;; return to 16 bit protected mode first
db 0xea
dd rombios32_10
Index: rombios.h
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
retrieving revision 1.3
diff -u -r1.3 rombios.h
--- rombios.h 3 Oct 2006 20:27:30 -0000 1.3
+++ rombios.h 8 Jan 2008 14:05:52 -0000
@@ -19,7 +19,7 @@
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/* define it to include QEMU specific code */
-//#define BX_QEMU
+#define BX_QEMU
#ifndef LEGACY
# define BX_ROMBIOS32 1
Index: rombios32.c
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
retrieving revision 1.8
diff -u -r1.8 rombios32.c
--- rombios32.c 3 Oct 2006 20:27:30 -0000 1.8
+++ rombios32.c 8 Jan 2008 14:05:54 -0000
@@ -606,7 +619,7 @@
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
- if (vendor_id == 0x8086 && device_id == 0x7000) {
+ if (vendor_id == 0x8086 && (device_id == 0x7000 || device_id == 0x27a0 || device_id == 0x27b9)) {
int i, irq;
uint8_t elcr[2];
@@ -679,7 +692,7 @@
d->bus, d->devfn, vendor_id, device_id);
switch(class) {
case 0x0101:
- if (vendor_id == 0x8086 && device_id == 0x7010) {
+ if (vendor_id == 0x8086 && (device_id == 0x7010 || device_id == 0x269e)) {
/* PIIX3 IDE */
pci_config_writew(d, 0x40, 0x8000); // enable IDE0
pci_config_writew(d, 0x42, 0x8000); // enable IDE1
@@ -852,6 +865,11 @@
int ioapic_id, i, len;
int mp_config_table_size;
+#ifdef BX_QEMU
+ if (smp_cpus <= 1)
+ return;
+#endif
+
#ifdef BX_USE_EBDA_TABLES
mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
#else
@@ -1116,6 +1134,23 @@
#endif
};
+/*
+ * ACPI 2.0 Root System Description Table (HPET)
+ */
+struct hpet_descriptor_rev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t hwblock_id;
+ uint8_t space_id;
+ uint8_t bit_width;
+ uint8_t bit_offset;
+ uint8_t access_width;
+ uint32_t address[2];
+ uint8_t seqnr;
+ uint16_t min_clock;
+ uint8_t flags;
+};
+
/* Values for Type in APIC_HEADER_DEF */
@@ -1214,9 +1249,10 @@
struct rsdt_descriptor_rev1 *rsdt;
struct fadt_descriptor_rev1 *fadt;
struct facs_descriptor_rev1 *facs;
+ struct hpet_descriptor_rev1 *hpet;
struct multiple_apic_table *madt;
uint8_t *dsdt;
- uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
+ uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, hpet_addr;
uint32_t acpi_tables_size, madt_addr, madt_size;
int i;
@@ -1250,6 +1286,10 @@
dsdt = (void *)(addr);
addr += sizeof(AmlCode);
+ hpet_addr = addr;
+ hpet = (void *)(addr);
+ hpet += sizeof(*hpet);
+
addr = (addr + 7) & ~7;
madt_addr = addr;
madt_size = sizeof(*madt) +
@@ -1313,6 +1354,14 @@
/* DSDT */
memcpy(dsdt, AmlCode, sizeof(AmlCode));
+ /* HPET */
+ memset(hpet, 0, sizeof(*hpet));
+ hpet->hwblock_id = cpu_to_le32(0x8086A201);
+ hpet->address[0] = cpu_to_le32(0xFED00000);
+ hpet->min_clock = cpu_to_le16(0x80);
+ acpi_build_table_header((struct acpi_table_header *)hpet,
+ "HPET", sizeof(*hpet));
+
/* MADT */
{
struct madt_processor_apic *apic;
@@ -1340,6 +1389,14 @@
acpi_build_table_header((struct acpi_table_header *)madt,
"APIC", madt_size);
}
+
+ /* PBLK (CPU information structure) */
+ {
+ uint32_t *pblk = (void*) (0x410);
+ *pblk = 0;
+ ((char*)pblk)[4] = 64; // L2 size;
+ ((char*)pblk)[5] = 0; // L3 size;
+ }
}
void rombios32_init(void)
