Andreas Färber a écrit :
Am 04.01.2013 22:29, schrieb Hervé Poussineau:
static const MemoryRegionOps piix4_pci_ops = {
- .old_portio = (MemoryRegionPortio[]) {
- {
- .offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
- .read = pci_up_read,
- },{
- .offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
- .read = pci_down_read,
- },{
- .offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
- .read = pci_features_read,
- .write = pciej_write,
- },{
- .offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
- .read = pcirmv_read,
- },
- PORTIO_END_OF_LIST()
+ .read = pci_read,
+ .write = pci_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
},
- .endianness = DEVICE_LITTLE_ENDIAN,
Ugh, question: Why is this changing Little Endian to native?
An error.
However, I was unable to find in the spec if this field is native on
little endian. Not that it changes anything for now, as x86 is little
endian...
I will respin patches, except those already in your memory-ioport branch.
Hervé
