[Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0

[Aurelien Jarno]

When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.

Reviewed-by: Eric Johnson <er...@mips.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
 target-mips/translate.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6281e70..d1fc5af 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12657,11 +12657,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, 
DisasContext *ctx, uint32_t opc,
     const char *opn = "ldx";
     TCGv t0;
 
-    if (rd == 0) {
-        MIPS_DEBUG("NOP");
-        return;
-    }
-
     check_dsp(ctx);
     t0 = tcg_temp_new();
 
-- 
1.7.10.4