On 10 December 2012 03:32, <d...@ertl.jp> wrote: > Fix a bug on the ARM GIC model where interrupts are not > set pending on the correct target CPUs when they are > triggered by writes to the Interrupt Set Enable or > Set Pending registers. > > Signed-off-by: Daniel Sangorrin <d...@ertl.jp>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Thanks -- applied to the arm-devs.next tree. -- PMM
