On 12/02/2012 06:57 AM, Andreas Färber wrote:
It uses a different capsbase and opregbase than the Xilinx device.
Signed-off-by: Liming Wang <walimis...@gmail.com>
Signed-off-by: Andreas Färber <andreas.faer...@web.de>
Cc: Igor Mitsyanko <i.mitsya...@samsung.com>
---
hw/usb/hcd-ehci-sysbus.c | 15 +++++++++++++++
hw/usb/hcd-ehci.h | 2 ++
2 Dateien geändert, 17 Zeilen hinzugefügt(+)
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 38e82bb..2ac61e6 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -103,10 +103,25 @@ static const TypeInfo ehci_xlnx_type_info = {
.class_init = ehci_xlnx_class_init,
};
+static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
+{
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
+
+ sec->capsbase = 0x0;
+ sec->opregbase = 0x40;
+}
Hi, Liming, where did you get value 0x40 for opregbase? My documentation
states that its 0x10 for Exynos4210 soc.
+
+static const TypeInfo ehci_exynos4210_type_info = {
+ .name = TYPE_EXYNOS4210_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_exynos4210_class_init,
+};
+
static void ehci_sysbus_register_types(void)
{
type_register_static(&ehci_type_info);
type_register_static(&ehci_xlnx_type_info);
+ type_register_static(&ehci_exynos4210_type_info);
}
type_init(ehci_sysbus_register_types)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index d8078f4..b8b6461 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -314,6 +314,8 @@ struct EHCIState {
bool int_req_by_async;
};
+#define TYPE_EXYNOS4210_EHCI "exynos4210-usb"
+
Maybe use a more descriptive name "exynos4210-usb-ehci" here, for
consistency with hcd-ehci-pci.c.
But anyway, I tested it, it works fine)
Reviewed-by: Igor Mitsyanko <i.mitsya...@samsung.com>
extern const VMStateDescription vmstate_ehci;
void usb_ehci_initfn(EHCIState *s, DeviceState *dev);
--
Mitsyanko Igor
ASWG, Moscow R&D center, Samsung Electronics
email: i.mitsya...@samsung.com
