> > > > Check permissions for the last byte first in unaligned slow_st > > > > accesses (patch from TeLeMan). > > > > > > Has it been checked that it's legal for all architectures and cannot > > > have any nasty side effect to do accesses in the reverse order ? Real > > > hardware do not ever seem to do this... > > > > For real hardware the store is a single operation. > > For PowerPC, at least, only aligned stores are defined as atomic. It's > absolutely legal for an implementation to split all non-atomic accesses > into smaller aligned accesses. And I guess it is the same for all
Depends how you're measuring atomicity. It's possible for an architecture could have non-atomic stores (w.r.t. other CPUs in an SMP system), but require that MMU faults restore state as it was before the faulting instruction executed. By my reading this is that case for x86. For ARM these checks are unnecessary and the previous code was acceptable. Quoting from the ARM architecture manual: " If a Data Abort occurs [...] the value of each memory location that the instruction stores to is: * unchanged if the memory system does not permit write access to the memory location * UNPREDICTABLE otherwise " There is also wording that explicitly allows the CPU to split an unaligned access into multiple smaller accesses. > One case that obviously can have nasty side effects is if doing > unaligned IO accesses ARM does not allow unaligned accesses to IO regions, so this should not be a problem there. Paul
