Signed-off-by: Michael Roth <mdr...@linux.vnet.ibm.com>
---
hw/msix.c | 12 ++++++++----
hw/pci.c | 5 +++++
hw/pci.h | 53 +++++++++++++++++++++++++++++-----------------------
hw/pci_internals.h | 28 ++++++++++++++-------------
4 files changed, 58 insertions(+), 40 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index 136ef09..117f5ed 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -271,17 +271,19 @@ int msix_init(struct PCIDevice *dev, unsigned short
nentries,
dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK;
- dev->msix_table = g_malloc0(table_size);
- dev->msix_pba = g_malloc0(pba_size);
+ dev->msix_table_size = table_size;
+ dev->msix_table = g_malloc0(dev->msix_table_size);
+ dev->msix_pba_size = pba_size;
+ dev->msix_pba = g_malloc0(dev->msix_pba_size);
dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
msix_mask_all(dev, nentries);
memory_region_init_io(&dev->msix_table_mmio, &msix_table_mmio_ops, dev,
- "msix-table", table_size);
+ "msix-table", dev->msix_table_size);
memory_region_add_subregion(table_bar, table_offset,
&dev->msix_table_mmio);
memory_region_init_io(&dev->msix_pba_mmio, &msix_pba_mmio_ops, dev,
- "msix-pba", pba_size);
+ "msix-pba", dev->msix_pba_size);
memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
return 0;
@@ -359,10 +361,12 @@ void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar,
MemoryRegion *pba_bar)
memory_region_destroy(&dev->msix_pba_mmio);
g_free(dev->msix_pba);
dev->msix_pba = NULL;
+ dev->msix_pba_size = 0;
memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
memory_region_destroy(&dev->msix_table_mmio);
g_free(dev->msix_table);
dev->msix_table = NULL;
+ dev->msix_table_size = 0;
g_free(dev->msix_entry_used);
dev->msix_entry_used = NULL;
dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
diff --git a/hw/pci.c b/hw/pci.c
index dceda0b..cfef76a 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -35,6 +35,11 @@
#include "msix.h"
#include "exec-memory.h"
+QIDL_ENABLE()
+
+QIDL_IMPLEMENT_PUBLIC(PCIDevice)
+QIDL_IMPLEMENT_PUBLIC(PCIBus)
+
//#define DEBUG_PCI
#ifdef DEBUG_PCI
# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
diff --git a/hw/pci.h b/hw/pci.h
index 241c1d8..e356fbd 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -187,37 +187,39 @@ typedef int (*MSIVectorUseNotifier)(PCIDevice *dev,
unsigned int vector,
MSIMessage msg);
typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
-struct PCIDevice {
+QIDL_DECLARE_PUBLIC(PCIDevice) {
DeviceState qdev;
/* PCI config space */
- uint8_t *config;
+ uint8_t *config \
+ q_size((pci_is_express(*obj) ? \
+ PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE));
/* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask. */
- uint8_t *cmask;
+ uint8_t q_immutable *cmask;
/* Used to implement R/W bytes */
- uint8_t *wmask;
+ uint8_t q_immutable *wmask;
/* Used to implement RW1C(Write 1 to Clear) bytes */
- uint8_t *w1cmask;
+ uint8_t q_immutable *w1cmask;
/* Used to allocate config space for capabilities. */
- uint8_t *used;
+ uint8_t q_immutable *used;
/* the following fields are read only */
PCIBus *bus;
- int32_t devfn;
- char name[64];
- PCIIORegion io_regions[PCI_NUM_REGIONS];
- AddressSpace bus_master_as;
+ int32_t q_property("addr", -1) devfn;
+ char q_string name[64];
+ PCIIORegion q_immutable io_regions[PCI_NUM_REGIONS];
+ AddressSpace q_immutable bus_master_as;
MemoryRegion bus_master_enable_region;
DMAContext *dma;
/* do not access the following fields */
- PCIConfigReadFunc *config_read;
- PCIConfigWriteFunc *config_write;
+ PCIConfigReadFunc q_immutable *config_read;
+ PCIConfigWriteFunc q_immutable *config_write;
/* IRQ objects for the INTA-INTD pins. */
qemu_irq *irq;
@@ -226,7 +228,10 @@ struct PCIDevice {
uint8_t irq_state;
/* Capability bits */
- uint32_t cap_present;
+ uint32_t \
+ q_property("multifunction", QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false) \
+ q_property("command_serr_enable", QEMU_PCI_CAP_SERR_BITNR, true) \
+ cap_present;
/* Offset of MSI-X capability in config space */
uint8_t msix_cap;
@@ -235,15 +240,17 @@ struct PCIDevice {
int msix_entries_nr;
/* Space to store MSIX table & pending bit array */
- uint8_t *msix_table;
- uint8_t *msix_pba;
+ int32_t msix_table_size;
+ uint8_t *msix_table q_size(msix_table_size);
+ int32_t msix_pba_size;
+ uint8_t *msix_pba q_size(msix_pba_size);
/* MemoryRegion container for msix exclusive BAR setup */
MemoryRegion msix_exclusive_bar;
/* Memory Regions for MSIX table and pending bit entries. */
MemoryRegion msix_table_mmio;
MemoryRegion msix_pba_mmio;
/* Reference-count for entries actually in use by driver. */
- unsigned *msix_entry_used;
+ unsigned q_immutable *msix_entry_used;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */
@@ -253,23 +260,23 @@ struct PCIDevice {
uint8_t msi_cap;
/* PCI Express */
- PCIExpressDevice exp;
+ PCIExpressDevice q_broken exp; /* TODO: qidl, is PCIEAERLog guest-visible?
*/
/* SHPC */
- SHPCDevice *shpc;
+ SHPCDevice q_broken *shpc; /* TODO: qidl, needed for pci-bridge support */
/* Location of option rom */
- char *romfile;
+ char q_property("romfile") *romfile;
bool has_rom;
MemoryRegion rom;
- uint32_t rom_bar;
+ uint32_t q_property("rombar", 1) rom_bar;
/* INTx routing notifier */
- PCIINTxRoutingNotifier intx_routing_notifier;
+ PCIINTxRoutingNotifier q_immutable intx_routing_notifier;
/* MSI-X notifiers */
- MSIVectorUseNotifier msix_vector_use_notifier;
- MSIVectorReleaseNotifier msix_vector_release_notifier;
+ MSIVectorUseNotifier q_immutable msix_vector_use_notifier;
+ MSIVectorReleaseNotifier q_immutable msix_vector_release_notifier;
};
void pci_register_bar(PCIDevice *pci_dev, int region_num,
diff --git a/hw/pci_internals.h b/hw/pci_internals.h
index 21d0ce6..bf40dc6 100644
--- a/hw/pci_internals.h
+++ b/hw/pci_internals.h
@@ -15,29 +15,31 @@
#define TYPE_PCI_BUS "PCI"
#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
-struct PCIBus {
+typedef struct PCIBus PCIBus;
+
+QIDL_DECLARE_PUBLIC(PCIBus) {
BusState qbus;
- PCIDMAContextFunc dma_context_fn;
- void *dma_context_opaque;
+ PCIDMAContextFunc q_immutable dma_context_fn;
+ void q_immutable *dma_context_opaque;
uint8_t devfn_min;
- pci_set_irq_fn set_irq;
- pci_map_irq_fn map_irq;
- pci_route_irq_fn route_intx_to_irq;
- pci_hotplug_fn hotplug;
+ pci_set_irq_fn q_immutable set_irq;
+ pci_map_irq_fn q_immutable map_irq;
+ pci_route_irq_fn q_immutable route_intx_to_irq;
+ pci_hotplug_fn q_immutable hotplug;
DeviceState *hotplug_qdev;
- void *irq_opaque;
- PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
- PCIDevice *parent_dev;
+ void q_immutable *irq_opaque;
+ PCIDevice q_elsewhere *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
+ PCIDevice q_elsewhere *parent_dev;
MemoryRegion *address_space_mem;
MemoryRegion *address_space_io;
- QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
- QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
+ QLIST_HEAD(, PCIBus) q_immutable child; /* this will be replaced by qdev
later */
+ QLIST_ENTRY(PCIBus) q_immutable sibling;/* this will be replaced by qdev
later */
/* The bus IRQ state is the logical OR of the connected devices.
Keep a count of the number of devices with raised IRQs. */
int nirq;
- int *irq_count;
+ int *irq_count q_size(nirq);
};
typedef struct PCIBridgeWindows PCIBridgeWindows;
--
1.7.9.5
