On 10/27/12 02:42, Peter Crosthwaite wrote:
>> Any chance the access you are seeing is at offset 0x68?
>
> 0x1a8. which for the opregbase + 0x068 for zynq so probably what you
> are thinking about.
Does the attached patch help?
cheers,
Gerd
>From 6a131b1476640c07317a6f44b5bb54ec53974414 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kra...@redhat.com>
Date: Mon, 29 Oct 2012 08:32:47 +0100
Subject: [PATCH] ehci: set extended capability pointer on pci only
Signed-off-by: Gerd Hoffmann <kra...@redhat.com>
---
hw/usb/hcd-ehci.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index a07beff..a35cbf2 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -2792,7 +2792,6 @@ static void usb_ehci_initfn(EHCIState *s, DeviceState
*dev, EHCIInfo *ei)
s->caps[0x06] = 0x00;
s->caps[0x07] = 0x00;
s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
- s->caps[0x09] = 0x68; /* EECP */
s->caps[0x0a] = 0x00;
s->caps[0x0b] = 0x00;
@@ -2880,6 +2879,8 @@ static int usb_ehci_pci_initfn(PCIDevice *dev)
s->irq = dev->irq[3];
s->dma = pci_dma_context(dev);
+ s->caps[0x09] = 0x68; /* EECP */
+
usb_ehci_initfn(s, DEVICE(dev), &c->ehci);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
--
1.7.1
