From: Peter A. G. Crosthwaite <peter.crosthwa...@petalogix.com>
Added linux smp support for the xilinx zynq platform (2x cpus are supported)
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwa...@petalogix.com>
---
Changed from v1:
Addressed PMM review
Shorted secondary bootloop using MVN instruction.
Used default reset secondary instead of custom one.
Rebased against QOM cpu developments.
Few whitespace fixes.
hw/xilinx_zynq.c | 57 ++++++++++++++++++++++++++++++++++++++++++-----------
1 files changed, 45 insertions(+), 12 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index 7e6c273..22a2bc5 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -30,6 +30,32 @@
#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
+#define SMP_BOOT_ADDR 0x0fff0000
+#define SMP_BOOTREG_ADDR 0xfffffff0
+
+/* Entry point for secondary CPU */
+static uint32_t zynq_smpboot[] = {
+ 0xe3e0000f, /* ldr r0, =0xfffffff0 (mvn r0, #15) */
+ 0xe320f002, /* wfe */
+ 0xe5901000, /* ldr r1, [r0] */
+ 0xe1110001, /* tst r1, r1 */
+ 0x0afffffb, /* beq <wfe> */
+ 0xe12fff11, /* bx r1 */
+ 0,
+};
+
+static void zynq_write_secondary_boot(ARMCPU *cpu,
+ const struct arm_boot_info *info)
+{
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(zynq_smpboot); n++) {
+ zynq_smpboot[n] = tswap32(zynq_smpboot[n]);
+ }
+ rom_add_blob_fixed("smpboot", zynq_smpboot, sizeof(zynq_smpboot),
+ SMP_BOOT_ADDR);
+}
+
static struct arm_boot_info zynq_binfo = {};
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
@@ -50,7 +76,7 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
const char *kernel_filename, const char
*kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- ARMCPU *cpu;
+ ARMCPU *cpus[2];
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
@@ -60,19 +86,21 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
qemu_irq pic[64];
NICInfo *nd;
int n;
- qemu_irq cpu_irq;
+ qemu_irq cpu_irq[2];
if (!cpu_model) {
cpu_model = "cortex-a9";
}
- cpu = cpu_arm_init(cpu_model);
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
+ for (n = 0; n < smp_cpus; n++) {
+ cpus[n] = cpu_arm_init(cpu_model);
+ if (!cpus[n]) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ irqp = arm_pic_init_cpu(cpus[n]);
+ cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
- irqp = arm_pic_init_cpu(cpu);
- cpu_irq = irqp[ARM_PIC_CPU_IRQ];
/* max 2GB ram */
if (ram_size > 0x80000000) {
@@ -103,11 +131,13 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000);
dev = qdev_create(NULL, "a9mpcore_priv");
- qdev_prop_set_uint32(dev, "num-cpu", 1);
+ qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, 0xF8F00000);
- sysbus_connect_irq(busdev, 0, cpu_irq);
+ for (n = 0; n < smp_cpus; n++) {
+ sysbus_connect_irq(busdev, n, cpu_irq[n]);
+ }
for (n = 0; n < 64; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
@@ -134,7 +164,10 @@ static void zynq_init(ram_addr_t ram_size, const char
*boot_device,
zynq_binfo.kernel_filename = kernel_filename;
zynq_binfo.kernel_cmdline = kernel_cmdline;
zynq_binfo.initrd_filename = initrd_filename;
- zynq_binfo.nb_cpus = 1;
+ zynq_binfo.nb_cpus = smp_cpus;
+ zynq_binfo.write_secondary_boot = zynq_write_secondary_boot;
+ zynq_binfo.smp_loader_start = SMP_BOOT_ADDR;
+ zynq_binfo.smp_bootreg_addr = SMP_BOOTREG_ADDR;
zynq_binfo.board_id = 0xd32;
zynq_binfo.loader_start = 0;
arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo);
@@ -145,7 +178,7 @@ static QEMUMachine zynq_machine = {
.desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
.init = zynq_init,
.use_scsi = 1,
- .max_cpus = 1,
+ .max_cpus = 2,
.no_sdcard = 1
};
--
1.7.0.4
