On Sat, Sep 17, 2011 at 05:28:16PM -0700, Eric Johnson wrote:
> The microMIPS SWP and SDP instructions do not modify GPRs. So their
> behavior is well defined when RD equals BASE. The MIPS Architecture
> Verification Programs (AVPs) check that they work as expected. This
> is required for AVPs to pass.
>
> Signed-off-by: Eric Johnson <er...@mips.com>
> ---
> target-mips/translate.c | 10 +++++++++-
> 1 files changed, 9 insertions(+), 1 deletions(-)
>
> The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641.
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index d5b1c76..82cf75b 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10034,7 +10034,7 @@ static void gen_ldst_pair (DisasContext *ctx,
> uint32_t opc, int rd,
> const char *opn = "ldst_pair";
> TCGv t0, t1;
>
> - if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) {
> + if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
> generate_exception(ctx, EXCP_RI);
> return;
> }
> @@ -10046,6 +10046,10 @@ static void gen_ldst_pair (DisasContext *ctx,
> uint32_t opc, int rd,
>
> switch (opc) {
> case LWP:
> + if (rd == base) {
> + generate_exception(ctx, EXCP_RI);
> + return;
> + }
> save_cpu_state(ctx, 0);
> op_ld_lw(t1, t0, ctx);
> gen_store_gpr(t1, rd);
> @@ -10067,6 +10071,10 @@ static void gen_ldst_pair (DisasContext *ctx,
> uint32_t opc, int rd,
> break;
> #ifdef TARGET_MIPS64
> case LDP:
> + if (rd == base) {
> + generate_exception(ctx, EXCP_RI);
> + return;
> + }
> save_cpu_state(ctx, 0);
> op_ld_ld(t1, t0, ctx);
> gen_store_gpr(t1, rd);
>
>
Thanks, applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net
