On 20 August 2012 17:43, Mark Phillips <mark.phill...@csr.com> wrote: > I have been experimenting with Sebastian's patches mentioned earlier > (http://git.rtems.org/rtems/tree/c/src/lib/libbsp/arm/lm3s69xx?id=e1ebfebf1bffe3e7731ac529409bd2576285467b) > and think I have found another major issue:-( > > My reading of the ARM documentation is that the SVC opcode should perform a > synchronous exception. > It doesn't, the calling code continues to execute asynchronously.
If true this would indeed be a significant bug. It's definitely not true for A/R profile cores... Do you have some test code /debug trace that demonstrates this? -- PMM
