Aurelien Jarno wrote: > Hi all, > > The patch below implements per-cpu decoding on the MIPS target. The > supported instruction set is defined by a set of flags. It assumes that > MIPS2 instructions are always supported. It also removes the check for > CP0C0_AT when setting MIPS_HFLAG_64 as it is now obsolete.
I expanded parts of it to (at least theoretically) cover the whole ISA space, renamed INSN -> ISA / ASE, since that's what we actually check for, and fixed a few misassumptions (e.g. Xcontext is MIPS3). Thiemo
