> > IIUC devices never register addresses on the master bus. The only thing > > that responds on that bus is the IOMMU. > > Generally yes, but these "intelligent masters" and their targets would > register on on both buses. The only case I can only think of is a > video grabber, it's frame memory could be accessed directly by other > IO devices.
Ah, I think we've got different interpretations of what "registering" a device involves. To a first approximation a master doesn't need to register with a bus at all. Slave devices can't/don't need to identify which master initiated the transaction. Plus all bus transactions are atomic w.r.t. other bus traffic, so no arbitration is needed. Masters will need to register with a bus insofar as they need to get a reference to identify which bus they're talking to. They don't generally reserve any bus address space though. Most devices are actually dual function master/slave devices, so already have a bus handle from registering the slave device. > > > For the Sparc64 PCI bus which has an IOMMU, a similar dual bus > > > arrangement would be needed. On PC/PPC systems the two buses would be > > > again one. > > > > PCI shouldn't need a dual bus setup. You just have one bus for PCI and > > one bus for CPU/memory. > > Then how would Sparc64 IOMMU intercept the device DMA? I'd think that > PCI bus mastering works similarly as in SBus, or doesn't it? A PCI host controller effectively consists of two bridges. The CPU->PCI bridge responds to requests on the CPU bus, using simple linear address translation to create PCI requests. The PCI->CPU bridge responds to requests on the PCI bus (ie. device DMA), using an IOMMU to translate these into CPU requests. The interesting bits of a generic bus infrastructure are the bridges between the busses, not the busses themselves. Conceptually each access starts on the bus local to that device (the system bus for the CPU, PCI bus for device DMA, etc), then recursively walks bus-bus bridges until it finds a device. Walking over a bridge is what causes address translation, and that translation is sensitive to direction. I admit I haven't figured out how to implement this efficiently. Paul
