Hi,
On Wed, 29 Aug 2007, Andreas Färber wrote:
> Am I right to assume that compiling with gcc3 will still work with your
> patch?
Yes.
> In that case your patch would enable qemu to run on gcc4-only platforms
> (where performance doesn't matter too much yet) while allowing to
> compile with gcc3 for performance reasons where necessary.
If necessary yes. The patch obviously would need to be changed to be
conditional not only on HOST_I386 but also on GCC version. Better to do
benchmarks first, if it's worthwhile.
> >The whole patch is against a 0.9.0-cvs version from 2007-07-09 (Alex
> >might know the exact checkout date), so chances are that it still
> >applies :)
>
> What do you mean with 0.9.0-cvs? The 0.9.0 GCC4 patches for OSX/Intel
Do you mean my patches?
> don't apply to HEAD possibly due to some inline assembler changes,
It seems target-z80 doesn't exist in CVS, apart from that there's a small
s/target_ulong/ppc_gpr_t/ in the target-ppc hunk. Otherwise it applies
just fine (I'll attach the patch against CVS, in case pine managed to
mangle it last time).
> and if merged manually resulted in a crash...
I just tested the attached patch with qemu fresh from CVS on HOST_I386
with target i386 (no kqemu, so it's really emulating), and target mipsel.
It works just fine. (gcc 4.1.2 for that matter)
Ciao,
Michael.
Index: Makefile.target
===================================================================
RCS file: /sources/qemu/qemu/Makefile.target,v
retrieving revision 1.194
diff -u -p -r1.194 Makefile.target
--- Makefile.target 26 Aug 2007 17:45:59 -0000 1.194
+++ Makefile.target 29 Aug 2007 10:29:42 -0000
@@ -125,6 +125,7 @@ endif
ifeq ($(ARCH),ppc)
CPPFLAGS+= -D__powerpc__
+OP_CFLAGS+= -fno-section-anchors
ifdef CONFIG_LINUX_USER
BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
endif
Index: softmmu_header.h
===================================================================
RCS file: /sources/qemu/qemu/softmmu_header.h,v
retrieving revision 1.15
diff -u -p -r1.15 softmmu_header.h
--- softmmu_header.h 23 May 2007 19:58:10 -0000 1.15
+++ softmmu_header.h 29 Aug 2007 10:29:42 -0000
@@ -250,14 +250,18 @@ static inline void glue(glue(st, SUFFIX)
: "r" (ptr),
/* NOTE: 'q' would be needed as constraint, but we could not use it
with T1 ! */
+#if DATA_SIZE == 1 || DATA_SIZE == 2
+ "q" (v),
+#else
"r" (v),
+#endif
"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
"i" (CPU_MEM_INDEX),
"m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
- : "%eax", "%ecx", "%edx", "memory", "cc");
+ : "%eax", "%edx", "memory", "cc");
}
#else
Index: target-alpha/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-alpha/cpu.h,v
retrieving revision 1.4
diff -u -p -r1.4 cpu.h
--- target-alpha/cpu.h 3 Jun 2007 21:02:37 -0000 1.4
+++ target-alpha/cpu.h 29 Aug 2007 10:29:43 -0000
@@ -278,6 +278,8 @@ struct CPUAlphaState {
* used to emulate 64 bits target on 32 bits hosts
*/
target_ulong t0, t1, t2;
+#elif defined(HOST_I386)
+ target_ulong t2;
#endif
/* */
double ft0, ft1, ft2;
Index: target-alpha/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-alpha/exec.h,v
retrieving revision 1.2
diff -u -p -r1.2 exec.h
--- target-alpha/exec.h 3 Jun 2007 17:44:36 -0000 1.2
+++ target-alpha/exec.h 29 Aug 2007 10:29:43 -0000
@@ -40,7 +40,11 @@ register struct CPUAlphaState *env asm(A
register uint64_t T0 asm(AREG1);
register uint64_t T1 asm(AREG2);
+#ifndef HOST_I386
register uint64_t T2 asm(AREG3);
+#else
+#define T2 (env->t2)
+#endif
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
Index: target-alpha/op_template.h
===================================================================
RCS file: /sources/qemu/qemu/target-alpha/op_template.h,v
retrieving revision 1.1
diff -u -p -r1.1 op_template.h
--- target-alpha/op_template.h 5 Apr 2007 06:58:33 -0000 1.1
+++ target-alpha/op_template.h 29 Aug 2007 10:29:43 -0000
@@ -28,7 +28,26 @@ void OPPROTO glue(op_reset_T, REG) (void
void OPPROTO glue(op_reset_FT, REG) (void)
{
+#ifdef HOST_PPC
+ /* We have a problem with HOST_PPC here:
+ We want this code:
+ glue(FT, REG) = 0;
+ unfortunately GCC4 notices that this stores (double)0.0 into
+ env->ft0 and emits that constant into the .rodata, and instructions
+ to load that zero from there. But that construct can't be parsed by dyngen.
+ We could add -ffast-math for compiling op.c, that would just make it generate
+ two stores of zeros into both words of ft0. But -ffast-math may have other
+ side-effects regarding the emulation. We could use __builtin_memset,
+ which perhaps would be the sanest. That relies on -O2 and our other options
+ to inline that memset, which currently it does, but who knows for how long.
+ So, we simply do that by hand, and a barely typesafe way :-/ */
+ union baeh { double d; unsigned int i[2];};
+ union baeh *p = (union baeh*)&(glue(FT, REG));
+ p->i[0] = 0;
+ p->i[1] = 0;
+#else
glue(FT, REG) = 0;
+#endif
RETURN();
}
Index: target-arm/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-arm/cpu.h,v
retrieving revision 1.30
diff -u -p -r1.30 cpu.h
--- target-arm/cpu.h 29 Jul 2007 17:57:26 -0000 1.30
+++ target-arm/cpu.h 29 Aug 2007 10:29:43 -0000
@@ -52,6 +52,9 @@ typedef uint32_t ARMReadCPFunc(void *opa
*/
typedef struct CPUARMState {
+#if defined(HOST_I386)
+ uint32_t t1;
+#endif
/* Regs for current mode. */
uint32_t regs[16];
/* Frequently accessed CPSR bits are stored separately for efficiently.
Index: target-arm/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-arm/exec.h,v
retrieving revision 1.12
diff -u -p -r1.12 exec.h
--- target-arm/exec.h 3 Jun 2007 17:44:36 -0000 1.12
+++ target-arm/exec.h 29 Aug 2007 10:29:43 -0000
@@ -23,7 +23,12 @@
register struct CPUARMState *env asm(AREG0);
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
+#ifndef HOST_I386
register uint32_t T2 asm(AREG3);
+#else
+#define T2 (env->t1)
+#endif
+
/* TODO: Put these in FP regs on targets that have such things. */
/* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */
Index: target-i386/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-i386/cpu.h,v
retrieving revision 1.45
diff -u -p -r1.45 cpu.h
--- target-i386/cpu.h 11 Jul 2007 22:48:58 -0000 1.45
+++ target-i386/cpu.h 29 Aug 2007 10:29:43 -0000
@@ -427,6 +427,8 @@ typedef struct CPUX86State {
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* temporaries if we cannot store them in host registers */
target_ulong t0, t1, t2;
+#elif defined(HOST_I386)
+ target_ulong t1;
#endif
/* standard registers */
Index: target-i386/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-i386/exec.h,v
retrieving revision 1.34
diff -u -p -r1.34 exec.h
--- target-i386/exec.h 26 Jun 2007 08:35:18 -0000 1.34
+++ target-i386/exec.h 29 Aug 2007 10:29:43 -0000
@@ -44,7 +44,11 @@ register struct CPUX86State *env asm(ARE
/* XXX: use unsigned long instead of target_ulong - better code will
be generated for 64 bit CPUs */
register target_ulong T0 asm(AREG1);
+#ifndef HOST_I386
register target_ulong T1 asm(AREG2);
+#else
+#define T1 (env->t1)
+#endif
register target_ulong T2 asm(AREG3);
/* if more registers are available, we define some registers too */
Index: target-mips/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-mips/cpu.h,v
retrieving revision 1.42
diff -u -p -r1.42 cpu.h
--- target-mips/cpu.h 23 Jun 2007 18:04:11 -0000 1.42
+++ target-mips/cpu.h 29 Aug 2007 10:29:43 -0000
@@ -60,7 +60,10 @@ struct CPUMIPSState {
target_ulong t0;
target_ulong t1;
target_ulong t2;
+#elif defined(HOST_I386)
+ target_ulong t1;
#endif
+
target_ulong HI, LO;
/* Floating point registers */
fpr_t fpr[32];
Index: target-mips/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-mips/exec.h,v
retrieving revision 1.30
diff -u -p -r1.30 exec.h
--- target-mips/exec.h 3 Jun 2007 17:44:36 -0000 1.30
+++ target-mips/exec.h 29 Aug 2007 10:29:43 -0000
@@ -17,7 +17,11 @@ register struct CPUMIPSState *env asm(AR
#else
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
+#ifndef HOST_I386
register target_ulong T2 asm(AREG3);
+#else
+#define T2 (env->t1)
+#endif
#endif
#if defined (USE_HOST_FLOAT_REGS)
Index: target-ppc/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-ppc/cpu.h,v
retrieving revision 1.49
diff -u -p -r1.49 cpu.h
--- target-ppc/cpu.h 11 Jul 2007 10:36:47 -0000 1.49
+++ target-ppc/cpu.h 29 Aug 2007 10:29:43 -0000
@@ -694,6 +694,8 @@ struct CPUPPCState {
* used to emulate 64 bits target on 32 bits hosts
*/
ppc_gpr_t t0, t1, t2;
+#elif defined(HOST_I386)
+ ppc_gpr_t t1;
#endif
ppc_avr_t t0_avr, t1_avr, t2_avr;
Index: target-ppc/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-ppc/exec.h,v
retrieving revision 1.22
diff -u -p -r1.22 exec.h
--- target-ppc/exec.h 11 Jul 2007 10:36:47 -0000 1.22
+++ target-ppc/exec.h 29 Aug 2007 10:29:43 -0000
@@ -40,7 +40,11 @@ register struct CPUPPCState *env asm(ARE
#else
register unsigned long T0 asm(AREG1);
register unsigned long T1 asm(AREG2);
+#ifndef HOST_I386
register unsigned long T2 asm(AREG3);
+#else
+#define T2 (env->t1)
+#endif
#endif
/* We may, sometime, need 64 bits registers on 32 bits target */
#if TARGET_GPR_BITS > HOST_LONG_BITS
Index: target-sparc/exec.h
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/exec.h,v
retrieving revision 1.19
diff -u -p -r1.19 exec.h
--- target-sparc/exec.h 3 Jun 2007 17:44:37 -0000 1.19
+++ target-sparc/exec.h 29 Aug 2007 10:29:43 -0000
@@ -32,9 +32,13 @@ register uint32_t T2 asm(AREG4);
#else
#define REGWPTR env->regwptr
+#ifndef HOST_I386
register uint32_t T2 asm(AREG3);
-#endif
#define reg_T2
+#else
+#define T2 (env->t2)
+#endif
+#endif
#endif
#define FT0 (env->ft0)
