On Fri, Feb 20, 2026 at 01:21:12PM -0500, Michael S. Tsirkin wrote:
> On Wed, Feb 04, 2026 at 05:09:29PM +0000, Jonathan Cameron wrote:
>
> ...
>
> > index 85694707e2e4..3c7ecd8c48bc 100644
> > --- a/hw/mem/cxl_type3.c
> > +++ b/hw/mem/cxl_type3.c
> > @@ -405,7 +405,7 @@ static void build_dvsecs(CXLType3Dev *ct3d)
> > dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
> > .cap = 0x26, /* 68B, IO, Mem, non-MLD */
> > .ctrl = 0x02, /* IO always enabled */
> > - .status = 0x26, /* same as capabilities */
> > + .status = ct3d->flitmode ? 0x6 : 0x26, /* lack of
> > 68B */
>
>
> would be clearer as:
>
> .status = 0x6 /* IO, Mem, non-MLD */ |
> ct3d->flitmode ? 0x0 : 0x20 /* 68B */
(ct3d->flitmode ? 0x0 : 0x20) naturally due to precedence.
>
>
> I picked this patch up, comment fixup can be a patch on top.
>
>
> --
> MST
