> > Hi, > > IIRC the word array thing is device specific, not really AXI stream. > I think the whole connection to AXI is a bit unfortunate,
Yes, so I think we can summaries the confusion here with AXI stream is completely unreleated to AXI. The connection between the two comes with the way low level signalling is handled. (e.g. the SRC_RDY and DST_RDY pins etc. etc.), thats common between AXI and AXI stream hence the shared name. This is of course completely irrelevant to QEMU. these devices > are pretty much the same devices that in other contexts where connected > to other bus standards. Xilinx choose to name them AXI-xxx and I used > the name in our models but I didn't really model anything that is AXI > stream specific.. > Theres not a lot to model. With the signalling stuff taken away, its pretty much just a unidirectional point-to-point data bus. There is the T_LAST bit, and the extended capabilities PMM mentioned. > >> There doesn't appear to be a notion of an address though. You could >> make all operations go to address 0 though but it makes me wonder if >> that's stretching the concept of DMA a bit too much. > > Yes, IMO we need a different abstraction.. > Seconded, and the other argument, is that the protocol should be usable for non-memory-access purposes (i.e. AXI stream sources and sinks do not have to be RAM, ROM etc). > Cheers
