On Wed, Dec 03, 2025 at 05:12:37PM +0000, Conor Dooley wrote: > On Sun, Nov 30, 2025 at 05:21:06PM +0800, Chao Liu wrote: > > The C908 processor is based on the RV64GCB[V] instruction > > set, compatible to RVA22 Profile and implements the XIE > > (XuanTie Instruction Extension) technology. > > > > Signed-off-by: Chao Liu <[email protected]> > > Suggested-by: LIU Zhiwei <[email protected]> > > --- > > target/riscv/cpu-qom.h | 2 + > > target/riscv/cpu.c | 43 +++++ > > target/riscv/th_csr.c | 380 ++++++++++++++++++++++++++++++++++++++++- > > 3 files changed, 424 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > > index 75f4e43408..1ddb5a6a6c 100644 > > --- a/target/riscv/cpu-qom.h > > +++ b/target/riscv/cpu-qom.h > > @@ -52,6 +52,8 @@ > > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > > #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") > > +#define TYPE_RISCV_CPU_THEAD_C908 RISCV_CPU_TYPE_NAME("thead-c908") > > +#define TYPE_RISCV_CPU_THEAD_C908V RISCV_CPU_TYPE_NAME("thead-c908v") > > #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > > #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") > > #define TYPE_RISCV_CPU_XIANGSHAN_NANHU > > RISCV_CPU_TYPE_NAME("xiangshan-nanhu") > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index d055ddf462..202ff130ee 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -3091,6 +3091,49 @@ static const TypeInfo riscv_cpu_type_infos[] = { > > #endif > > ), > > > > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908, TYPE_RISCV_VENDOR_CPU, > > + .misa_mxl_max = MXL_RV64, > > + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, > > + .priv_spec = PRIV_VERSION_1_12_0, > > + > > + /* ISA extensions */ > > + .cfg.ext_xtheadba = true, > > + .cfg.ext_xtheadbb = true, > > + .cfg.ext_xtheadbs = true, > > + .cfg.ext_xtheadcmo = true, > > + .cfg.ext_xtheadcondmov = true, > > + .cfg.ext_xtheadmac = true, > > + .cfg.ext_xtheadmemidx = true, > > + .cfg.ext_xtheadmempair = true, > > + .cfg.ext_xtheadsync = true, > > + .cfg.ext_zba = true, > > + .cfg.ext_zbb = true, > > + .cfg.ext_zbc = true, > > + .cfg.ext_zbs = true, > > + .cfg.ext_zkt = true, > > + .cfg.ext_zbkc = true, > > + .cfg.ext_zicsr = true, > > + .cfg.ext_zifencei = true, > > + .cfg.ext_zihintpause = true, > > + .cfg.ext_zicbom = true, > > + .cfg.ext_zicboz = true, > > + .cfg.ext_zfh = true, > > + .cfg.ext_xtheadfmv = true, > > + .cfg.ext_xtheadfmemidx = true, > > + .cfg.pmp = true, > > I think Svpbmt is missing here, both it and the T-Head MAEE stuff are > supported on the k230. What I will end up merging into mainline for the
Whoops, should have specified that I meant the mainline linux kernel. > k230 uses Svpbmt instead of MAEE.
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