Add OpenRISC Programmable Interrupt Controller.
Signed-off-by: Jia Liu <pro...@gmail.com>
---
hw/openrisc_pic.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++
target-openrisc/cpu.h | 2 ++
2 files changed, 52 insertions(+)
diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c
index 1c20790..76bd792 100644
--- a/hw/openrisc_pic.c
+++ b/hw/openrisc_pic.c
@@ -25,4 +25,54 @@
/* Reset PIC */
void cpu_openrisc_pic_reset(CPUOpenRISCState *env)
{
+ env->picmr = 0x00000000;
+ env->picsr = 0x00000000;
+}
+
+/* OpenRISC pic handler */
+static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
+{
+ CPUOpenRISCState *env = (CPUOpenRISCState *)opaque;
+ int i;
+ uint32_t irq_bit = 1 << irq;
+
+ if (irq > 31 || irq < 0) {
+ return;
+ }
+
+ if (level) {
+ env->picsr |= irq_bit;
+ } else {
+ env->picsr &= ~irq_bit;
+ }
+
+ for (i = 0; i < 32; i++) {
+ if ((env->picsr && (1 << i)) && (env->picmr && (1 << i))) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ env->picsr &= ~(1 << i);
+ }
+ }
+}
+
+void cpu_openrisc_pic_init(CPUOpenRISCState *env)
+{
+ int i;
+ qemu_irq *qi;
+ qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, env, NR_IRQS);
+
+ for (i = 0; i < NR_IRQS; i++) {
+ env->irq[i] = qi[i];
+ }
+}
+
+void cpu_openrisc_store_picmr(CPUOpenRISCState *env, uint32_t value)
+{
+ env->picmr |= value;
+}
+
+void cpu_openrisc_store_picsr(CPUOpenRISCState *env, uint32_t value)
+{
+ env->picsr &= ~value;
}
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 568eb74..27f705b 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -328,6 +328,8 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
target_ulong address,
#if !defined(CONFIG_USER_ONLY)
void cpu_openrisc_pic_reset(CPUOpenRISCState *env);
+void cpu_openrisc_store_picsr(CPUOpenRISCState *env, uint32_t value);
+void cpu_openrisc_store_picmr(CPUOpenRISCState *env, uint32_t value);
void cpu_openrisc_timer_reset(CPUOpenRISCState *env);
--
1.7.9.5
