For KVM mode, the privilege mode should not include M-mode, and the
initial value should be set to S-mode. Additionally, a following patch
adds the implementation of putting the vCPU privilege mode to KVM.
When the vCPU runs for the first time, QEMU will first put the privilege
state to KVM. If the initial value is set to M-mode, KVM will encounter
an error.
In addition, this patch introduces the 'mp_state' field to RISC-V
vCPUs, following the convention used by KVM on x86. The 'mp_state'
reflects the multiprocessor state of a vCPU, and is used to control
whether the vCPU is runnable by KVM. Randomly select one CPU as the
boot CPU.
Signed-off-by: Xie Bo <x...@ultrarisc.com>
---
target/riscv/cpu.c | 17 ++++++++++++++++-
target/riscv/cpu.h | 2 ++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 09ded6829a..57b8c421bd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -38,6 +38,7 @@
#include "kvm/kvm_riscv.h"
#include "tcg/tcg-cpu.h"
#include "tcg/tcg.h"
+#include "hw/boards.h"
/* RISC-V CPU definitions */
static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
@@ -1031,18 +1032,32 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType
type)
#ifndef CONFIG_USER_ONLY
uint8_t iprio;
int i, irq, rdzero;
+ static int boot_cpu_index = -1;
#endif
CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
CPURISCVState *env = &cpu->env;
+ MachineState *ms = MACHINE(qdev_get_machine());
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj, type);
}
#ifndef CONFIG_USER_ONLY
env->misa_mxl = mcc->misa_mxl_max;
- env->priv = PRV_M;
+ if (kvm_enabled()) {
+ env->priv = PRV_S;
+ } else {
+ env->priv = PRV_M;
+ }
+ if (boot_cpu_index < 0) {
+ boot_cpu_index = g_random_int() % ms->smp.cpus;
+ }
+ if (cs->cpu_index == boot_cpu_index) {
+ env->mp_state = KVM_MP_STATE_RUNNABLE;
+ } else {
+ env->mp_state = KVM_MP_STATE_STOPPED;
+ }
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) {
/*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 51e49e03de..4b1c5bf0e4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -256,6 +256,8 @@ struct CPUArchState {
#endif
target_ulong priv;
+ /* Current multiprocessor state of this vCPU. */
+ uint32_t mp_state;
/* CSRs for execution environment configuration */
uint64_t menvcfg;
target_ulong senvcfg;
--
2.43.0
