As with part 1, several issues have been addressed with v2 but some remain.
* From "Implement modify SSR": HVX context management is moved out of this
series (it is no longer present in any of part 1, 2, 3). It can be
revisited after these land.
Issues remaining, to be considered for v3:
* "Implement wait helper" - move hexagon_wait_thread() to op_helper.c?
* "Implement arch_{s, g}et_{thread, system}_reg()" - remove
arch_[sg]et_system_reg() entirely?
* "Implement setprio, resched" - use ~0 for BESTWAIT_PRIO
* "Add exec-start-addr prop" - don't use ULL for UINT32
* "Define system, guest reg names" - fix last five reg names
* "Add TLB, k0 {un,}lock" - revisit design with suggestion from Richard
* "Define gen_precise_exception" - reword commit subject
Brian Cain (37):
target/hexagon: Implement ciad helper
target/hexagon: Implement {c,}swi helpers
target/hexagon: Implement iassign{r,w} helpers
target/hexagon: Implement start/stop helpers, soft reset
target/hexagon: Implement modify SSR
target/hexagon: Implement {g,s}etimask helpers
target/hexagon: Implement wait helper
target/hexagon: Implement get_exe_mode()
target/hexagon: Implement arch_get_system_reg()
target/hexagon: Implement arch_{s,g}et_{thread,system}_reg()
target/hexagon: Add representation to count cycles
target/hexagon: Add implementation of cycle counters
target/hexagon: Implement modify_syscfg()
target/hexagon: Implement hex_tlb_entry_get_perm()
target/hexagon: Implement hex_tlb_lookup_by_asid()
target/hexagon: Implement software interrupt
target/hexagon: Implement exec_interrupt, set_irq
target/hexagon: Implement hexagon_tlb_fill()
target/hexagon: Implement siad inst
target/hexagon: Implement hexagon_resume_threads()
target/hexagon: Implement setprio, resched
target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()
target/hexagon: Add exec-start-addr prop
target/hexagon: extend hexagon_cpu_mmu_index() for sysemu
target/hexagon: Decode trap1, rte as COF
target/hexagon: Implement hexagon_find_last_irq()
target/hexagon: Implement modify_ssr, resched, pending_interrupt
target/hexagon: Add pkt_ends_tb to translation
target/hexagon: Add next_PC, {s,g}reg writes
target/hexagon: Add implicit sysreg writes
target/hexagon: Define system, guest reg names
target/hexagon: initialize sys/guest reg TCGvs
target/hexagon: Add TLB, k0 {un,}lock
target/hexagon: Define gen_precise_exception()
target/hexagon: Add TCG overrides for transfer insts
target/hexagon: Add support for loadw_phys
target/hexagon: Add pcycle setting functionality
Matheus Tavares Bernardino (2):
target/hexagon: add simple cpu_exec_reset and pointer_wrap
target/hexagon: Add guest reg reading functionality
target/hexagon/cpu.h | 13 +-
target/hexagon/cpu_helper.h | 21 +-
target/hexagon/gen_tcg.h | 7 -
target/hexagon/gen_tcg_sys.h | 25 ++
target/hexagon/helper.h | 7 +-
target/hexagon/hexswi.h | 17 +
target/hexagon/internal.h | 2 +
target/hexagon/sys_macros.h | 8 +-
target/hexagon/translate.h | 5 +
target/hexagon/reg_fields_def.h.inc | 11 +
linux-user/hexagon/cpu_loop.c | 7 +
target/hexagon/cpu.c | 349 ++++++++++++++++++++-
target/hexagon/cpu_helper.c | 358 ++++++++++++++++++++-
target/hexagon/decode.c | 14 +
target/hexagon/genptr.c | 7 +-
target/hexagon/hex_mmu.c | 84 ++++-
target/hexagon/hexswi.c | 256 +++++++++++++++
target/hexagon/machine.c | 2 +-
target/hexagon/op_helper.c | 430 ++++++++++++++++++++++++--
target/hexagon/translate.c | 304 ++++++++++++++++--
target/hexagon/hex_common.py | 3 +
target/hexagon/imported/encode_pp.def | 1 +
target/hexagon/imported/ldst.idef | 3 +
23 files changed, 1848 insertions(+), 86 deletions(-)
create mode 100644 target/hexagon/hexswi.h
create mode 100644 target/hexagon/hexswi.c
--
2.34.1
