On 8/27/25 09:26, Richard Henderson wrote:
On 8/10/25 09:42, Richard Henderson wrote:
x86 doesn't directly support 8-bit vector shifts, so we have
some 2 to 5 insn expansions. With VGF2P8AFFINEQB, we can do
it in 1 insn, plus a (possibly shared) constant load.
r~
Richard Henderson (3):
cpuinfo/i386: Detect GFNI as an AVX extension
tcg/i386: Add INDEX_op_x86_vgf2p8affineqb_vec
tcg/i386: Use vgf2p8affineqb for MO_8 vector shifts
host/include/i386/host/cpuinfo.h | 1 +
include/qemu/cpuid.h | 3 ++
util/cpuinfo-i386.c | 1 +
tcg/i386/tcg-target-opc.h.inc | 1 +
tcg/i386/tcg-target.c.inc | 81 ++++++++++++++++++++++++++++++--
5 files changed, 83 insertions(+), 4 deletions(-)
Ping.
I don't know the target-independent part of TCG, but arithmetic right
shift by 7 probably should keep using pcmpgtb?
There's also a typo in patch 1 (s/NF/FN/):
+#ifndef bit_GNFI
+#define bit_GNFI (1 << 8)
+#endif
Paolo
