So far, just extend the data type and check access; do not yet
produce the 128-bit AT format result.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/cpu.h | 14 +++++++-------
target/arm/internals.h | 1 +
target/arm/helper.c | 17 ++++++++++++++++-
target/arm/tcg/cpregs-at.c | 4 +++-
4 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f7b861c6d6..57e298363c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -415,15 +415,14 @@ typedef struct CPUArchState {
};
uint64_t hpfar_el2;
uint64_t hstr_el2;
- union { /* Translation result. */
+ /* Translation result. */
+ union {
struct {
- uint64_t _unused_par_0;
- uint64_t par_ns;
- uint64_t _unused_par_1;
- uint64_t par_s;
- };
- uint64_t par_el[4];
+ uint64_t HOST_ENDIAN_FIELDS(par_ns, _unused_par_0);
+ }; /* aa32 */
+ Int128 par_el1; /* aa64 */
};
+ uint64_t par_s; /* aa32 */
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
@@ -1703,6 +1702,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define SCR_HXEN (1ULL << 38)
#define SCR_TRNDR (1ULL << 40)
#define SCR_ENTP2 (1ULL << 41)
+#define SCR_D128EN (1ULL << 47)
#define SCR_GPF (1ULL << 48)
#define SCR_NSE (1ULL << 62)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 08e2acdb99..31934435db 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -232,6 +232,7 @@ FIELD(VTCR, SL2, 33, 1)
#define HCRX_CMOW (1ULL << 9)
#define HCRX_MCE2 (1ULL << 10)
#define HCRX_MSCEN (1ULL << 11)
+#define HCRX_D128EN (1ULL << 17)
#define HPFAR_NS (1ULL << 63)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0282e41c59..fb37d0674b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -498,6 +498,20 @@ static CPAccessResult access_tacr(CPUARMState *env, const
ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+static CPAccessResult access_d128(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ int el = arm_current_el(env);
+
+ if (el <= 1 && !(arm_hcrx_el2_eff(env) & HCRX_D128EN)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ if (el <= 2 && !(env->cp15.scr_el3 & SCR_D128EN)) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ return CP_ACCESS_OK;
+}
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
{
ARMCPU *cpu = env_archcpu(env);
@@ -3270,7 +3284,8 @@ static void define_par_register(ARMCPU *cpu)
.name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
.access = PL1_RW, .fgt = FGT_PAR_EL1,
- .fieldoffset = offsetof(CPUARMState, cp15.par_el[1])
+ .type = ARM_CP_128BIT, .access128fn = access_d128,
+ .fieldoffset = offsetof(CPUARMState, cp15.par_el1)
};
static ARMCPRegInfo par64_reginfo[2] = {
diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c
index 398a61d398..ebf5a04a11 100644
--- a/target/arm/tcg/cpregs-at.c
+++ b/target/arm/tcg/cpregs-at.c
@@ -322,6 +322,7 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE);
bool for_el3 = false;
ARMSecuritySpace ss;
+ uint64_t par64;
switch (ri->opc2 & 6) {
case 0:
@@ -359,7 +360,8 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
}
ss = for_el3 ? arm_security_space(env) : arm_security_space_below_el3(env);
- env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss);
+ par64 = do_ats_write(env, value, access_type, mmu_idx, ss);
+ env->cp15.par_el1 = int128_make64(par64);
}
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.43.0
