Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 3 +++ target/arm/tcg/translate-a64.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 392a0a264f..ee8b870e17 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -52,6 +52,7 @@ enum { ARM_CP_GCSPUSHX = 0x000a, ARM_CP_GCSPOPX = 0x000b, ARM_CP_GCSPOPCX = 0x000c, + ARM_CP_GCSSS1 = 0x000d, /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST = 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index 3236f607f3..51fc8298af 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -125,6 +125,9 @@ static const ARMCPRegInfo gcs_reginfo[] = { { .name = "GCSPOPM", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 7, .opc2 = 1, .access = PL0_R, .type = ARM_CP_GCSPOPM }, + { .name = "GCSSS1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 7, .opc2 = 2, + .access = PL0_W, .type = ARM_CP_GCSSS1 }, { .name = "GCSPUSHX", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 7, .opc2 = 4, .access = PL1_W, .accessfn = access_gcspushx, .fgt = FGT_NGCSEPP, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e9a57bc077..d97d9bfcb7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2635,6 +2635,31 @@ static void gen_gcspopx(DisasContext *s) tcg_gen_addi_i64(gcspr, addr, 8); } +static void gen_gcsss1(DisasContext *s, int rt) +{ + TCGv_i64 gcspr = cpu_gcspr[s->current_el]; + int mmuidx = core_gcs_mem_index(s->mmu_idx); + MemOp mop = finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 inptr = cpu_reg(s, rt); + TCGv_i64 cmp = tcg_temp_new_i64(); + TCGv_i64 new = tcg_temp_new_i64(); + TCGv_i64 old = tcg_temp_new_i64(); + TCGLabel *fail_label = + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSSS1, rt)); + + /* Compute the valid cap entry that the new stack must have. */ + tcg_gen_deposit_i64(cmp, inptr, tcg_constant_i64(1), 0, 12); + /* Compute the in-progress cap entry for the old stack. */ + tcg_gen_deposit_i64(new, gcspr, tcg_constant_i64(5), 0, 3); + + /* Swap the valid cap the with the in-progress cap. */ + tcg_gen_atomic_cmpxchg_i64(old, inptr, cmp, new, mmuidx, mop); + tcg_gen_brcond_i64(TCG_COND_NE, old, cmp, fail_label); + + /* The new stack had a valid cap: change gcspr. */ + tcg_gen_andi_i64(gcspr, inptr, ~7); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2946,6 +2971,11 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspopx(s); } return; + case ARM_CP_GCSSS1: + if (s->gcs_en) { + gen_gcsss1(s, rt); + } + return; default: g_assert_not_reached(); } -- 2.43.0