[RFC 08/11] hw/arm/smmuv3: Enable secure-side stage 2 TLB invalidations

[Tao Tang]

This change expands the secure command queue's capabilities by adding
two commands for managing secure stage 2 translation caches, as defined
by the Arm SMMUv3 architecture.

The following commands are now processed by the secure command queue:

- CMD_TLBI_S_S2_IPA: Invalidates secure stage 2 TLB entries by IPA for
a given secure VMID.
- CMD_TLBI_S_S12_VMALL: The secure equivalent of VMALLS12E1, this
invalidates all stage 1 and stage 2 entries for a specific secure
VMID.

The command handler verifies that these commands are issued only via the
secure queue and that secure stage 2 functionality is supported by the
model, raising an illegal command error otherwise.

This will be followed by a refactoring of the Configuration and
Translation lookup caches, paving the final path for enabling the
end-to-end processing of secure transactions.

Signed-off-by: Tao Tang <tangtao1...@phytium.com.cn>
---
 hw/arm/smmuv3-internal.h |  4 ++++
 hw/arm/smmuv3.c          | 20 ++++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 852186cea4..82821cbbcc 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -391,6 +391,8 @@ typedef enum SMMUCommandType {
     SMMU_CMD_RESUME          = 0x44,
     SMMU_CMD_STALL_TERM,
     SMMU_CMD_SYNC,
+    SMMU_CMD_TLBI_S_S12_VMALL  = 0x58,
+    SMMU_CMD_TLBI_S_S2_IPA     = 0x5a,
 } SMMUCommandType;
 
 static const char *cmd_stringify[] = {
@@ -419,6 +421,8 @@ static const char *cmd_stringify[] = {
     [SMMU_CMD_RESUME]          = "SMMU_CMD_RESUME",
     [SMMU_CMD_STALL_TERM]      = "SMMU_CMD_STALL_TERM",
     [SMMU_CMD_SYNC]            = "SMMU_CMD_SYNC",
+    [SMMU_CMD_TLBI_S_S12_VMALL] = "SMMU_CMD_TLBI_S_S12_VMALL",
+    [SMMU_CMD_TLBI_S_S2_IPA]   = "SMMU_CMD_TLBI_S_S2_IPA",
 };
 
 static inline const char *smmu_cmd_string(SMMUCommandType type)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 69b19754f1..5f28e27503 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1591,6 +1591,26 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, bool 
is_secure)
              */
             smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2, false);
             break;
+        case SMMU_CMD_TLBI_S_S2_IPA:
+            if (!is_secure || !STAGE2_SUPPORTED(s) ||
+                    (SECURE_IMPLEMENTED(s) && SECURE_S2_SUPPORTED(s))) {
+                cmd_error = SMMU_CERROR_ILL;
+                break;
+            }
+            smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2, true);
+            break;
+        case SMMU_CMD_TLBI_S_S12_VMALL:
+            if (!is_secure || !STAGE2_SUPPORTED(s) ||
+                    (SECURE_IMPLEMENTED(s) && SECURE_S2_SUPPORTED(s))) {
+                cmd_error = SMMU_CERROR_ILL;
+                break;
+            }
+
+            int vmid = CMD_VMID(&cmd);
+            trace_smmuv3_cmdq_tlbi_s12_vmid(vmid);
+            smmu_inv_notifiers_all(&s->smmu_state);
+            smmu_iotlb_inv_vmid(bs, vmid);
+            break;
         case SMMU_CMD_TLBI_EL3_ALL:
         case SMMU_CMD_TLBI_EL3_VA:
         case SMMU_CMD_TLBI_EL2_ALL:
-- 
2.34.1