On Fri, Jul 25, 2025 at 02:27:59PM +0300, Michael Tokarev wrote:
> On 13.07.2025 12:27, Akihiko Odaki wrote:
> > Fix issues in PCIe SR-IOV configuration register handling that caused
> > inconsistent internal state due to improper write mask handling and
> > incorrect migration behavior.
> >
> > Two main problems were identified:
> >
> > 1. VF Enable bit write mask handling:
> > pcie_sriov_config_write() incorrectly assumed that its val parameter
> > was already masked, causing it to ignore the actual write mask.
> > This led to the VF Enable bit being processed even when masked,
> > resulting in incorrect VF registration/unregistration.
> >
> > 2. Migration state inconsistency:
> > pcie_sriov_pf_post_load() unconditionally called register_vfs()
> > regardless of the VF Enable bit state, creating inconsistent
> > internal state when VFs should not be enabled. Additionally,
> > it failed to properly update the NumVFs write mask based on
> > the current configuration.
> >
> > Root cause analysis revealed that both functions relied on incorrect
> > special-case assumptions instead of properly reading and consuming
> > the actual configuration values. This change introduces a unified
> > consume_config() function that reads actual configuration values and
> > synchronize the internal state without special-case assumptions.
> >
> > The solution only adds register read overhead in non-hot-path code
> > while ensuring correct SR-IOV state management across configuration
> > writes and migration scenarios.
> >
> > Fixes: 5e7dd17e4348 ("pcie_sriov: Remove num_vfs from PCIESriovPF")
> > Fixes: f9efcd47110d ("pcie_sriov: Register VFs after migration")
> > Reported-by: Corentin BAYET <corentin.ba...@reversetactics.com>
> > Signed-off-by: Akihiko Odaki <od...@rsg.ci.i.u-tokyo.ac.jp>
>
> This issue has been assigned two CVEs, CVE-2025-54566 and CVE-2025-54567.
>
> Should we apply this fix for 10.1 and to stable-10.0 series too?
>
> Thanks,
>
> /mjt
sure
