Hi, This series is based on another series dedicated to cleaning up the legacy cache models:
https://lore.kernel.org/qemu-devel/20250711102143.1622339-1-zhao1....@intel.com/ And this series focuses only on improvements to the named CPU models: * Add cache model for Intel CPUs (and YongFeng). * Enable 0x1f CPUID leaf for specific Intel CPUs, which already have this leaf on host by default. You can also find the patches at here (branch: cache-model-v3.0-rebase- 07-10-2025): https://gitlab.com/zhao.liu/qemu/-/tree/cache-model-v3.0-rebase-07-10-2025?ref_type=heads Change Log ========== Changes since RFC (20250423114702.1529340-1-zhao1....@intel.com): * Split CPUID fixes into another series. * Since TDX was merged, rebase and rename 0x1f property to "x-force-cpuid-0x1f". (Igor) * Include cache model for YongFeng from Ewai. Intel Cache Model ================= AMD has supports cache model for a long time. And this feature strats from the Eduardo's idea [1]. Unfortunately, Intel does not support this, and I have received some feedback (from Tejus on mail list [2] and kvm forum, and from Jason). Additionally, after clearly defining the cache topology for QEMU's cache model, outdated cache models can easily raise more questions. For example, the default legacy cache model's L3 is per die, but SPR's real L3 is per socket. Users may question how the L3 topology changes when multiple dies are created (discussed with Daniel on [3]). So, in this series, I have added cache models for SRF, GNR, and SPR (because these are the only machines I can find at the moment :-) ). Note that the cache models are based on the Scalable Performance (SP) version, and the Xeon Advanced Performance (AP) version may have different cache sizes. However, SP is sufficient as the default cache model baseline. In the future, I will consider adding additional parameters in "smp-cache" to adjust cache sizes to meet different needs. [1]: https://lore.kernel.org/qemu-devel/20180320175427.GU3417@localhost.localdomain/ [2]: https://lore.kernel.org/qemu-devel/6766ac1f-96d1-41f0-aaeb-ce4158662...@nutanix.com/ [3]: https://lore.kernel.org/qemu-devel/zktrsddygrfzv...@redhat.com/ 0x1f CPUID by default (for some CPUs) ===================================== Once the cache model can be clearly defined, another issue is the topology. Currently, the cache topology is actually tied to the CPU topology. However, in recent Intel CPUs (from cascadelake-AP - 2nd xeon [4]), CPU topology information is primarily expressed using the 0x1f leaf. Due to compatibility issues and historical reasons, the Guest's 0x1f is not unconditionally exposed. The discrepancy between having 0x1f on the Host but not on the Guest does indeed cause problems (Manish mentioned in [5]). Manish and Xiaoyao (for TDX) both attempted to enable 0x1f by default for Intel CPUs [6] [7], but following Igor's suggestion, it is more appropriate to enable it by default only for certain CPU models [8]. So, as I update the CPU model at this time, I think it's time to revisit the community's idea. I enable the 0x1f leaf for SRF, GNR and SPR by default for better emulation of real silicons. Change Log ========== Changes Since v1: * Polish the note and enable 0x1f leaf for YongFeng. * Add R-b/T-b tags. Reference ========= [4]: https://lore.kernel.org/qemu-devel/zpowsky4xe%2f98...@intel.com/ [5]: https://lore.kernel.org/qemu-devel/ph0pr02mb738410511bf51b12db09be6cf6...@ph0pr02mb7384.namprd02.prod.outlook.com/ [6]: https://lore.kernel.org/qemu-devel/20240722101859.47408-1-manish.mis...@nutanix.com/ [7]: https://lore.kernel.org/qemu-devel/20240813033145.279307-1-xiaoyao...@intel.com/ [8]: https://lore.kernel.org/qemu-devel/20240723170321.0ef78...@imammedo.users.ipa.redhat.com/ [9]: https://lore.kernel.org/qemu-devel/20250401130205.2198253-34-xiaoyao...@intel.com/ Thanks and Best Regards, Zhao --- Ewan Hai (1): i386/cpu: Introduce cache model for YongFeng Manish Mishra (1): i386/cpu: Add a "x-force-cpuid-0x1f" property Zhao Liu (7): i386/cpu: Introduce cache model for SierraForest i386/cpu: Introduce cache model for GraniteRapids i386/cpu: Introduce cache model for SapphireRapids i386/cpu: Enable 0x1f leaf for SierraForest by default i386/cpu: Enable 0x1f leaf for GraniteRapids by default i386/cpu: Enable 0x1f leaf for SapphireRapids by default i386/cpu: Enable 0x1f leaf for YongFeng by default target/i386/cpu.c | 405 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 405 insertions(+) -- 2.34.1
