move som machine define to virt.h and define avec feature and status bit. Use the IOCSRF_AVEC bit for avdance interrupt controller drivers avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN. and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN.
[1]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c Signed-off-by: Song Gao <gaos...@loongson.cn> --- hw/loongarch/virt.c | 4 ++++ include/hw/loongarch/virt.h | 20 ++++++++++++++++++++ target/loongarch/cpu.h | 21 --------------------- 3 files changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index b15ada2078..6a169d4824 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -574,6 +574,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, break; case FEATURE_REG: ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); + /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ + ret |= BIT(IOCSRF_AVEC); if (kvm_enabled()) { ret |= BIT(IOCSRF_VM); } @@ -603,6 +605,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } + /* enable avec default */ + ret |= BIT_ULL(IOCSRM_AVEC_EN); break; default: g_assert_not_reached(); diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 602feab0f0..cc6656619d 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -13,6 +13,26 @@ #include "hw/block/flash.h" #include "hw/loongarch/boot.h" +#define IOCSRF_TEMP 0 +#define IOCSRF_NODECNT 1 +#define IOCSRF_MSI 2 +#define IOCSRF_EXTIOI 3 +#define IOCSRF_CSRIPI 4 +#define IOCSRF_FREQCSR 5 +#define IOCSRF_FREQSCALE 6 +#define IOCSRF_DVFSV1 7 +#define IOCSRF_GMOD 9 +#define IOCSRF_VM 11 +#define IOCSRF_AVEC 15 + +#define VERSION_REG 0x0 +#define FEATURE_REG 0x8 +#define VENDOR_REG 0x10 +#define CPUNAME_REG 0x20 +#define MISC_FUNC_REG 0x420 +#define IOCSRM_EXTIOI_EN 48 +#define IOCSRM_EXTIOI_INT_ENCODE 49 +#define IOCSRM_AVEC_EN 51 #define LOONGARCH_MAX_CPUS 256 #define VIRT_FWCFG_BASE 0x1e020000UL diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 9538e8d61d..56fc4a1459 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -21,27 +21,6 @@ #include "cpu-csr.h" #include "cpu-qom.h" -#define IOCSRF_TEMP 0 -#define IOCSRF_NODECNT 1 -#define IOCSRF_MSI 2 -#define IOCSRF_EXTIOI 3 -#define IOCSRF_CSRIPI 4 -#define IOCSRF_FREQCSR 5 -#define IOCSRF_FREQSCALE 6 -#define IOCSRF_DVFSV1 7 -#define IOCSRF_GMOD 9 -#define IOCSRF_VM 11 - -#define VERSION_REG 0x0 -#define FEATURE_REG 0x8 -#define VENDOR_REG 0x10 -#define CPUNAME_REG 0x20 -#define MISC_FUNC_REG 0x420 -#define IOCSRM_EXTIOI_EN 48 -#define IOCSRM_EXTIOI_INT_ENCODE 49 - -#define IOCSR_MEM_SIZE 0x428 - #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ -- 2.34.1
