On Sun, 22 Jun 2025 at 00:52, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu-features.h | 55 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 4452e7c21e..650abcb054 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -931,6 +931,11 @@ static inline bool isar_feature_aa64_sve2(const
> ARMISARegisters *id)
> return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
> }
>
> +static inline bool isar_feature_aa64_sve2p1(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) >= 2;
> +}
> +
> static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
> {
> return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
> @@ -976,6 +981,11 @@ static inline bool isar_feature_aa64_sve_f64mm(const
> ARMISARegisters *id)
> return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
> }
>
> +static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, B16B16) != 0;
> +}
> +
> static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
> {
> return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
> @@ -991,6 +1001,51 @@ static inline bool isar_feature_aa64_sme_fa64(const
> ARMISARegisters *id)
> return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
> }
>
> +static inline bool isar_feature_aa64_sme2(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, SMEVER) != 0;
> +}
> +
> +static inline bool isar_feature_aa64_sme2p1(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, SMEVER) >= 2;
> +}
> +
> +static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id)
> +{
> + return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id);
> +}
I think we should put these "utility" functions that are
testing for a combination of architectural features in their
own section of this header, in the same way that we separate
out 'Feature tests for "does this exist in either 32-bit or 64-bit?"'.
(I assume the reason we want them rather than just having the
caller open-code the "sme2 && i64i64" is so we can use them in
a macro or something later on?)
> +
> +static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id)
> +{
> + return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id);
> +}
> +
> +static inline bool isar_feature_aa64_sme2_b16b16(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, B16B16) != 0;
> +}
This is FEAT_SME_B16B16, not FEAT_SME2_B16B16; we should follow the
architectural feature name in our function name here, I think.
> +
> +static inline bool isar_feature_aa64_sme2_f16f16(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F16F16) != 0;
> +}
Similarly, sme_f16f16.
> +
> +static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)
> +{
> + return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);
> +}
> +
> +static inline bool isar_feature_aa64_sme2_or_sve2p1(const ARMISARegisters
> *id)
> +{
> + return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2p1(id);
> +}
> +
> +static inline bool isar_feature_aa64_sme2p1_or_sve2p1(const ARMISARegisters
> *id)
> +{
> + return isar_feature_aa64_sme2p1(id) || isar_feature_aa64_sve2p1(id);
> +}
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
