On 6/16/25 12:20 PM, Jonathan Cameron wrote:
> On Fri, 13 Jun 2025 15:44:43 +0100
> Shameer Kolothum <shameerali.kolothum.th...@huawei.com> wrote:
>
>> Although this change does not affect functionality at present, it is
> Patch title says PCIe. This check is vs PCI host bridge.
>
> No idea which one you wanted, but if it is PCIe needs to be
> TYPC_PCIE_HOST_BRIDGE from pcie_host.h not the pci_host.h one
> I think.
I think we need TYPE_PCI_HOST_BRIDGE as we want to check against pxb
pci-bridge/pci_expander_bridge.c: .parent = TYPE_PCI_HOST_BRIDGE,
Besides the commit title/desc suggested by Jonathan you may also refine
the error msg which can stem now from 2 different causes
Thanks
Eric
>
>> required when we add support for user-creatable SMMUv3 devices in
>> future patches.
>>
>> Tested-by: Nathan Chen <nath...@nvidia.com>
>> Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
>> ---
>> hw/arm/smmu-common.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
>> index f39b99e526..7890aa12c1 100644
>> --- a/hw/arm/smmu-common.c
>> +++ b/hw/arm/smmu-common.c
>> @@ -20,6 +20,7 @@
>> #include "trace.h"
>> #include "exec/target_page.h"
>> #include "hw/core/cpu.h"
>> +#include "hw/pci/pci_bridge.h"
>> #include "hw/qdev-properties.h"
>> #include "qapi/error.h"
>> #include "qemu/jhash.h"
>> @@ -937,7 +938,8 @@ static void smmu_base_realize(DeviceState *dev, Error
>> **errp)
>> g_free, g_free);
>> s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
>>
>> - if (s->primary_bus) {
>> + if (s->primary_bus &&
>> object_dynamic_cast(OBJECT(s->primary_bus)->parent,
>> + TYPE_PCI_HOST_BRIDGE)) {
>> pci_setup_iommu(s->primary_bus, &smmu_ops, s);
>> } else {
>> error_setg(errp, "SMMU is not attached to any PCI bus!");
