Re: [PATCH v1 01/15] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry

[Yi Liu]

On 2025/6/6 18:04, Zhenzhong Duan wrote:

In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry
of rid2pasid, then it was extended to get any pasid entry. So a new name
vtd_ce_get_pasid_entry is better to match what it actually does.

No functional change intended.

Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--d...@eviden.com>
---
  hw/i386/intel_iommu.c | 14 +++++++-------
  1 file changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Yi Liu <yi.l....@intel.com>

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 69d72ad35c..f0b1f90eff 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -944,7 +944,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
      return 0;
  }

-static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s,

+static int vtd_ce_get_pasid_entry(IntelIOMMUState *s,
                                        VTDContextEntry *ce,
                                        VTDPASIDEntry *pe,
                                        uint32_t pasid)
@@ -1025,7 +1025,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s,
      VTDPASIDEntry pe;

if (s->root_scalable) {

-        vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
+        vtd_ce_get_pasid_entry(s, ce, &pe, pasid);
          if (s->flts) {
              return VTD_PE_GET_FL_LEVEL(&pe);
          } else {
@@ -1048,7 +1048,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s,
      VTDPASIDEntry pe;

if (s->root_scalable) {

-        vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
+        vtd_ce_get_pasid_entry(s, ce, &pe, pasid);
          return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9;
      }

@@ -1116,7 +1116,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,

      VTDPASIDEntry pe;

if (s->root_scalable) {

-        vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
+        vtd_ce_get_pasid_entry(s, ce, &pe, pasid);
          if (s->flts) {
              return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR;
          } else {
@@ -1522,7 +1522,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s,
       * has valid rid2pasid setting, which includes valid
       * rid2pasid field and corresponding pasid entry setting
       */
-    return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID);
+    return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID);
  }

/* Map a device to its corresponding domain (context-entry) */

@@ -1611,7 +1611,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s,
      VTDPASIDEntry pe;

if (s->root_scalable) {

-        vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
+        vtd_ce_get_pasid_entry(s, ce, &pe, pasid);
          return VTD_SM_PASID_ENTRY_DID(pe.val[1]);
      }

@@ -1687,7 +1687,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VTDContextEntry *ce,

      int ret;

if (s->root_scalable) {

-        ret = vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
+        ret = vtd_ce_get_pasid_entry(s, ce, &pe, pasid);
          if (ret) {
              /*
               * This error is guest triggerable. We should assumt PT

a typo. not related to this patch though.

--
Regards,
Yi Liu