Introduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is supported:
+-----+ +-----------------------+ +-------+
| IPI | --> | CPUINTC | <-- | Timer |
+-----+ +-----------------------+ +-------+
^ ^ ^
| | |
+---------+ +----------+ +---------+ +-------+
| EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
+---------+ +----------+ +---------+ +-------+
^ ^
| |
+---------+ +---------+
| PCH-PIC | | PCH-MSI |
+---------+ +---------+
^ ^ ^
| | |
+---------+ +---------+ +---------+
| Devices | | PCH-LPC | | Devices |
+---------+ +---------+ +---------+
^
|
+---------+
| Devices |
+---------+
We can see more about AVECINTC on linux driver code[1]
and loongarch msg interrupts on volI 6.2 Message-Interrupts
Tested the code using the virion-net NIC, but there's a bit of a problem so
far, the NIC doesn't seem to be working correctly, there's a lot of dmesg prints
'
[ 44.068699] virtio_net virtio0 eth0: NETDEV WATCHDOG: CPU: 3: transmit queue
0 timed out 30500 ms
[ 44.069472] virtio_net virtio0 eth0: TX timeout on queue: 0, sq: output.0,
vq: 0x1, name: output.0, 30500000 usecs ago
'
So the series with a title 'RFC'
the start scripts is kernel.sh at[3]
[1]:
https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c
[2]:
https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
[3]:
https://github.com/gaosong715/qemu/releases/download/pull-loongarch-20250514/kernel.sh
Feel free to point out any flaws!
thanks.
Song Gao
Song Gao (10):
hw/loongarch: add a new type iocsr read for Avdance interrupt
controller
loongarch: add virt feature avecintc support
loongarch: add a advance interrupt controller device
target/loongarch: add msg interrupt CSR registers
hw/loongarch: AVEC controller add a MemoryRegion
hw/loongarch: Implement avec controller imput and output pins
hw/loongarch: connect pch_msi controller to avec controller
hw/loongarch: Implement avec set_irq
target/loongarch: loongarch CPU supoort avec irqs
target/loongarch: cpu_do_interrupt support msg interrupt.
hw/intc/Kconfig | 3 +
hw/intc/loongarch_avec.c | 152 +++++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1 +
hw/loongarch/virt.c | 95 +++++++++++++++++--
include/hw/intc/loongarch_avec.h | 36 ++++++++
include/hw/loongarch/virt.h | 10 ++
target/loongarch/cpu-csr.h | 2 +
target/loongarch/cpu.c | 53 ++++++++++-
target/loongarch/cpu.h | 15 ++-
target/loongarch/machine.c | 5 +
11 files changed, 362 insertions(+), 11 deletions(-)
create mode 100644 hw/intc/loongarch_avec.c
create mode 100644 include/hw/intc/loongarch_avec.h
--
2.34.1
