On Wed, Jun 04 2025, Shameerali Kolothum Thodi
<shameerali.kolothum.th...@huawei.com> wrote:
>> -----Original Message-----
>> From: Cornelia Huck <coh...@redhat.com>
>> Sent: Wednesday, June 4, 2025 1:36 PM
>> To: Shameerali Kolothum Thodi
>> <shameerali.kolothum.th...@huawei.com>; eric.auger....@gmail.com;
>> eric.au...@redhat.com; qemu-devel@nongnu.org; qemu-...@nongnu.org;
>> kvm...@lists.linux.dev; peter.mayd...@linaro.org;
>> richard.hender...@linaro.org; alex.ben...@linaro.org; m...@kernel.org;
>> oliver.up...@linux.dev; seb...@redhat.com; arm...@redhat.com;
>> berra...@redhat.com; abolo...@redhat.com; jdene...@redhat.com
>> Cc: ag...@csgraf.de; shahu...@redhat.com; mark.rutl...@arm.com;
>> phi...@linaro.org; pbonz...@redhat.com
>> Subject: RE: [PATCH v3 00/10] kvm/arm: Introduce a customizable aarch64
>> KVM host model
>>
>> On Wed, Jun 04 2025, Shameerali Kolothum Thodi
>> <shameerali.kolothum.th...@huawei.com> wrote:
>>
>> >> -----Original Message-----
>> >> From: Cornelia Huck <coh...@redhat.com>
>> >> Sent: Tuesday, June 3, 2025 4:15 PM
>> >> To: Shameerali Kolothum Thodi
>> >> <shameerali.kolothum.th...@huawei.com>; eric.auger....@gmail.com;
>> >> eric.au...@redhat.com; qemu-devel@nongnu.org; qemu-
>> a...@nongnu.org;
>> >> kvm...@lists.linux.dev; peter.mayd...@linaro.org;
>> >> richard.hender...@linaro.org; alex.ben...@linaro.org;
>> m...@kernel.org;
>> >> oliver.up...@linux.dev; seb...@redhat.com; arm...@redhat.com;
>> >> berra...@redhat.com; abolo...@redhat.com; jdene...@redhat.com
>> >> Cc: ag...@csgraf.de; shahu...@redhat.com; mark.rutl...@arm.com;
>> >> phi...@linaro.org; pbonz...@redhat.com
>> >> Subject: RE: [PATCH v3 00/10] kvm/arm: Introduce a customizable
>> aarch64
>> >> KVM host model
>> >>
>> >> On Tue, May 27 2025, Cornelia Huck <coh...@redhat.com> wrote:
>> >> > The conversion functions are not at fault here, but we're missing
>> >> > registers. If we have MIDR and friends writable, they show up in the
>> >> > masks returned by the kernel, but they are not present in the kernel's
>> >> > sysreg file where we generate our definitions from, and
>> >> > kvm_idx_to_idregs_idx() asserts instead of returning an error, which
>> >> > is kind of suboptimal...
>> >> >
>> >> > So I see two possible ways to fix this:
>> >> > - add MIDR and friends to the kernel's sysreg file
>> >> > - add MIDR and friends in QEMU's cpu-sysregs.h.inc file, and only
>> append
>> >> > generated definitions there
>> >> >
>> >> > First option means one more round trip, second options has more
>> >> > potential for messing things up if we keep stuff local to QEMU.
>> >>
>> >> With the patch below, things work for me with a 6.15+ kernel. It's a bit
>> >
>> > Yes works for me too now. Thanks.
>>
>> Thanks for checking.
>>
>> >
>> >> messy, though, and raises questions (how do we want to handle those
>> regs
>> >> across accelerators, for example, or how we can make sure that the code
>> is
>> >> more robust when registers are added.)
>> >>
>> >> My biggest question, however, is how this interacts with the framework
>> to
>> >> provide lists of MIDR/REVIDR/AIDR for errata management. The hack
>> below
>> >> adds properties to configure those regs, I guess we'd want to suppress
>> >> adding the props in order to avoid conflicts.
>> >
>> > Not sure how this impacts the errata management though. My initial take
>> on
>> > this was, user will provide a list of target CPU ids through command line
>> and
>> > that will be used to set the target CPUs for errata management(if kernel
>> > supports it).
>> >
>> > Eg:
>> > -machine virt,.., x-target-impl-cpus=0xMIDR1:0xREVIDR1-0xMIDR2:REVIDR2
>>
>> I'm a bit confused by the range, I'd rather expect a list of tuples,
>> e.g. <midr>:<revidr>,<midr>:<revidr>, ...
>
> Hmm..is the concern here is the format or the number of entries?
Format of the command line; number of entries is something we can change
later.
>
>>
>> >
>> > And these will be stored in,
>> >
>> > #define MAX_TARGET_IMPL_CPUS 4
>> > typedef struct TargetImplCpu {
>> > uint32_t midr;
>> > uint32_t revidr;
>>
>> Isn't revidr a 64 bit value?
>
> Yes. In fact they both are, though MIDR only uses 32 bits now. Will change.
It probably should also have aidr, just to be safe. (Even if triplets on
the command line will be a bit ugly.)
>
>>
>> > } TargetImplCpu;
>> >
>> >
>> > Please see the initial (a hack for testing kernel) implementation here,
>> >
>> https://github.com/hisilicon/qemu/commit/a393c1180274c73d34f32eaab66
>> 764a874a9ad31
>> >
>> > Please let me know if there is a better/preferred way of obtaining this
>> > target CPU list from user.
>>
>> I'm mostly wondering about conflicting values between "we make MIDR et
>> al. writable, so we have a value different from what the host sees" and
>> "we provide a list of possible values to the guest, so it can prepare
>> for running on those hosts". Do we want to be able to provide a common
>> set to the guest, and then enlighten it with the list of systems that it
>> actually *might* run on? A benefit would be that it could always observe
>> the same (configured) register entries, regardless where it runs (needs
>> more plumbing in QEMU, I think.) We'd also need to be clear about what
>> we'd require (i.e. do we expect that both the real host values and the
>> configured values are present in the list?)
>
> The expectation from kernel is that when target errata CPUs are specified,
> it includes the current host CPU Ids as well. We could check to see the list
> includes
> the host one. But I am not sure how we can validate the complete list provided
> by user though. I think, the onus of deciding which platforms this Guest VM
> is
> going to run during its life time and specifying that correctly is with the
> user.
My question was more along the line of "if the user configures MIDR to
something different from the actual host values, do they need to include
that modified value in the list of target cpus as well?" If we disallow
changing MIDR, we'd naturally sidestep that issue.
>
>>
>> Not sure if the machine level is the right place to configure this, or
>> if it needs to go to the cpu options. While it is a machine-wide
>> configuration, it also means that we configure some cpu features in two
>> different places (even if they serve a different purpose.)
>
> I exploited MachineState for ease of hacking 😊. But not sure this belongs to
> CPU
> either as it is very specific to KVM is enabled, supported kernel etc.
That's an interesting question :) I think we can keep it with the
machine state for now until we figure out more details -- it's more
important to actually test it out with real life scenarios.
>
>> We could also choose to not expose properties for MIDR and friends at
>> all, even if they are writable.
>>
>
> Does that mean Qemu figures out all the supported target Ids based on the
> Host CPU Ids?
I think the target ids always need to be figured out and provided by the
user (as only they can possibly have an idea on where that guest might
end up running.) The question is more whether we should give the user
the means to directly configure the regs for a certain instance.
