On 5/29/2025 3:47 AM, Alejandro Jimenez wrote:
> Fix an off-by-one error in the definition of AMDVI_IR_PHYS_ADDR_MASK. The
> current definition masks off the most significant bit of the Interrupt Table
> Root ptr i.e. it only generates a mask with bits [50:6] set. See the AMD I/O
> Virtualization Technology (IOMMU) Specification for the Interrupt Table
> Root Pointer[51:6] field in the Device Table Entry format.
> 
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Alejandro Jimenez <alejandro.j.jime...@oracle.com>

I found this issue last week when I was going through the code!Thanks for 
fixing.

Reviewed-by: Vasant Hegde <vasant.he...@amd.com>

-Vasant


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