Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote:
> From: Michael Kowal <ko...@linux.ibm.com>
>
> Writes to the Flush Control registers were logged as invalid
> when they are allowed. Clearing the unsupported want_cache_disable
> feature is supported, so don't log an error in that case.
>
> Signed-off-by: Michael Kowal <ko...@linux.ibm.com>
> ---
> hw/intc/pnv_xive2.c | 36 ++++++++++++++++++++++++++++++++----
> 1 file changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index 3c26cd6b77..c9374f0eee 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -1411,7 +1411,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr
> offset,
> /*
> * ESB cache updates (not modeled)
> */
> - /* case VC_ESBC_FLUSH_CTRL: */
> + case VC_ESBC_FLUSH_CTRL:
> + if (val & VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE) {
> + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx
> + " value 0x%"PRIx64" bit[2] poll_want_cache_disable",
> + offset, val);
> + return;
> + }
> + break;
> case VC_ESBC_FLUSH_POLL:
> xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |=
> VC_ESBC_FLUSH_CTRL_POLL_VALID;
> /* ESB update */
> @@ -1427,7 +1434,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr
> offset,
> /*
> * EAS cache updates (not modeled)
> */
> - /* case VC_EASC_FLUSH_CTRL: */
> + case VC_EASC_FLUSH_CTRL:
> + if (val & VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE) {
> + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx
> + " value 0x%"PRIx64" bit[2] poll_want_cache_disable",
> + offset, val);
> + return;
> + }
> + break;
> case VC_EASC_FLUSH_POLL:
> xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |=
> VC_EASC_FLUSH_CTRL_POLL_VALID;
> /* EAS update */
> @@ -1466,7 +1480,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr
> offset,
> break;
>
>
> - /* case VC_ENDC_FLUSH_CTRL: */
> + case VC_ENDC_FLUSH_CTRL:
> + if (val & VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE) {
> + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx
> + " value 0x%"PRIx64" bit[2] poll_want_cache_disable",
> + offset, val);
> + return;
> + }
> + break;
> case VC_ENDC_FLUSH_POLL:
> xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |=
> VC_ENDC_FLUSH_CTRL_POLL_VALID;
> break;
> @@ -1687,7 +1708,14 @@ static void pnv_xive2_ic_pc_write(void *opaque, hwaddr
> offset,
> pnv_xive2_nxc_update(xive, watch_engine);
> break;
>
> - /* case PC_NXC_FLUSH_CTRL: */
> + case PC_NXC_FLUSH_CTRL:
> + if (val & PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE) {
> + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx
> + " value 0x%"PRIx64" bit[2] poll_want_cache_disable",
> + offset, val);
> + return;
> + }
> + break;
> case PC_NXC_FLUSH_POLL:
> xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |=
> PC_NXC_FLUSH_CTRL_POLL_VALID;
> break;
