On Mon, May 12, 2025 at 7:53 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Allow using RISCVCPUDef to replicate all the logic of custom .instance_init
> functions. To simulate inheritance, merge the child's RISCVCPUDef with
> the parent and then finally move it to the CPUState at the end of
> TYPE_RISCV_CPU's own instance_init function.
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 4 ++++
> target/riscv/cpu.c | 42 +++++++++++++++++++++++++++++++++++++-
> target/riscv/kvm/kvm-cpu.c | 6 ++++++
> 3 files changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7edefc80d73..f9ba305e3ad 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -539,6 +539,10 @@ struct ArchCPU {
>
> typedef struct RISCVCPUDef {
> RISCVMXL misa_mxl_max; /* max mxl for this cpu */
> + uint32_t misa_ext;
> + int priv_spec;
> + int32_t vext_spec;
> + RISCVCPUConfig cfg;
> } RISCVCPUDef;
>
> /**
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddade8a4370..7864c7e27c6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -73,6 +73,13 @@ bool riscv_cpu_option_set(const char *optname)
> return g_hash_table_contains(general_user_opts, optname);
> }
>
> +static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig
> *src)
> +{
> +#define BOOL_FIELD(x) dest->x |= src->x;
> +#define TYPED_FIELD(type, x, default_) if (src->x != default_) dest->x =
> src->x;
> +#include "cpu_cfg_fields.h.inc"
> +}
> +
> #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
>
> @@ -434,7 +441,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool
> is_32_bit)
> }
>
> static void set_satp_mode_max_supported(RISCVCPU *cpu,
> - uint8_t satp_mode)
> + int satp_mode)
> {
> bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> @@ -1479,6 +1486,16 @@ static void riscv_cpu_init(Object *obj)
> cpu->cfg.cboz_blocksize = 64;
> cpu->env.vext_ver = VEXT_VERSION_1_00_0;
> cpu->cfg.max_satp_mode = -1;
> +
> + env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
> + riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);
> +
> + if (mcc->def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {
> + cpu->env.priv_ver = mcc->def->priv_spec;
> + }
> + if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
> + cpu->env.vext_ver = mcc->def->vext_spec;
> + }
> }
>
> static void riscv_bare_cpu_init(Object *obj)
> @@ -3087,6 +3104,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
> const void *data)
> assert(def->misa_mxl_max <= MXL_RV128);
> mcc->def->misa_mxl_max = def->misa_mxl_max;
> }
> + if (def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {
> + assert(def->priv_spec <= PRIV_VERSION_LATEST);
> + mcc->def->priv_spec = def->priv_spec;
> + }
> + if (def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
> + assert(def->vext_spec != 0);
> + mcc->def->vext_spec = def->vext_spec;
> + }
> + mcc->def->misa_ext |= def->misa_ext;
> +
> + riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg);
> }
>
> if (!object_class_is_abstract(c)) {
> @@ -3193,6 +3221,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .instance_init = (initfn), \
> .class_data = &(const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .cfg.max_satp_mode = -1, \
> }, \
> }
>
> @@ -3203,6 +3234,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .instance_init = (initfn), \
> .class_data = &(const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .cfg.max_satp_mode = -1, \
> }, \
> }
>
> @@ -3213,6 +3247,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .instance_init = (initfn), \
> .class_data = &(const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .cfg.max_satp_mode = -1, \
> }, \
> }
>
> @@ -3223,6 +3260,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .instance_init = (initfn), \
> .class_data = &(const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> + .cfg.max_satp_mode = -1, \
> }, \
> }
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index cd82b29567c..03f9b36f0c3 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -2004,10 +2004,16 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = {
> #if defined(TARGET_RISCV32)
> .class_data = &(const RISCVCPUDef) {
> .misa_mxl_max = MXL_RV32,
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED,
> + .cfg.max_satp_mode = -1,
> },
> #elif defined(TARGET_RISCV64)
> .class_data = &(const RISCVCPUDef) {
> .misa_mxl_max = MXL_RV64,
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> + .vext_spec = RISCV_PROFILE_ATTR_UNUSED,
> + .cfg.max_satp_mode = -1,
> },
> #endif
> }
> --
> 2.49.0
>
