On 5/7/25 11:40 PM, Philippe Mathieu-Daudé wrote:
On 8/5/25 01:14, Pierrick Bouvier wrote:
Add runtime helpers for target and config queries.
Note: This will be reimplemented later [1] using proper information in
TargetInfo. Meanwhile, just add a simple implementation.
[1]
https://patchew.org/QEMU/20250424222112.36194-1-phi...@linaro.org/20250424222112.36194-19-phi...@linaro.org/
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
---
meson.build | 2 +-
include/qemu/target-info.h | 14 +++++
target-info.c | 117 +++++++++++++++++++++++++++++++++++++
3 files changed, 132 insertions(+), 1 deletion(-)
+bool target_mips(void)
I know this is the same lowercase name, but maybe we could consider
directly using target_mips32() instead of keeping the technical debt
of having TARGET_MIPS defined for both 32 and 64-bit targets.
Thankfully we cleared that with recent targets (i.e. LoongArch or
RISC-V -- AVR is a bit different, since 8-bit AVR and AVR32 are
distinct architectures).
For x86 we often use 'x86' as any of (i386, x86_64, amd64), maybe
we can introduce target_x86() too.
+{
+#ifdef TARGET_MIPS
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_mips64(void)
+{
+#ifdef TARGET_MIPS64
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_loongarch64(void)
+{
+#ifdef TARGET_LOONGARCH64
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_riscv32(void)
+{
+#ifdef TARGET_RISCV32
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_riscv64(void)
+{
+#ifdef TARGET_RISCV64
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_ppc(void)
Ditto, target_ppc32()?
+{
+#ifdef TARGET_PPC
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_ppc64(void)
+{
+#ifdef TARGET_ppc64
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_has_kvm(void)
+{
+#ifdef CONFIG_KVM
+ return true;
+#else
+ return false;
+#endif
+}
I simply tried to reflect existing TARGET_* (so there is no
TARGET_PPC32, which is incoherent with having TARGET_RISCV{,32,64}).
For the long term, I think we should aim for a 1-1 mapping with
SysEmuTarget instead, which is *coherent*. As well, we'll probably want
a way to identify target base architecture, like target_base_arm(),
target_base_i386(), ..., which will include 32 and 64 bits variants.
Since patches for TargetInfo bringing target_arch() are not there yet, I
didn't want to bring all the material for a new bike shed, so I simply
followed existing TARGET_*. I hope we can have this whole conversation
on another dedicated series, once upstream TargetInfo will contain a
target_arch field.
