From: Tim Lee <timlee660...@gmail.com>
Sent: Wednesday, May 7, 2025 5:19 PM
To: faro...@suse.de; lviv...@redhat.com; pbonz...@redhat.com;
wuhao...@google.com; CS20 KFTing <kft...@nuvoton.com>; CS20 CHLi30
<chl...@nuvoton.com>
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Tim Lee <timlee660...@gmail.com>
Subject: [v2] tests/qtest: Add qtest for NPCM8XX PSPI module
- Created qtest to check initialization of registers in PSPI Module
- Implemented test into Build File
Tested:
./build/tests/qtest/npcm8xx-pspi_test
Signed-off-by: Tim Lee <timlee660...@gmail.com>
---
Changes since v1:
- MAINTAINERS file not need to change
- Add comment for copyright/license information
- Correct CTL registers to use 16 bits
- Remove printf() in test cases
tests/qtest/meson.build | 3 +
tests/qtest/npcm8xx_pspi-test.c | 118 ++++++++++++++++++++++++++++++++
2 files changed, 121 insertions(+)
create mode 100644 tests/qtest/npcm8xx_pspi-test.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index
3136d15e0f..88672a8b00 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -210,6 +210,8 @@ qtests_npcm7xx = \
'npcm7xx_watchdog_timer-test',
'npcm_gmac-test'] + \
(slirp.found() ? ['npcm7xx_emc-test'] : [])
+qtests_npcm8xx = \
+ ['npcm8xx_pspi-test']
qtests_aspeed = \
['aspeed_hace-test',
'aspeed_smc-test',
@@ -257,6 +259,7 @@ qtests_aarch64 = \
(config_all_accel.has_key('CONFIG_TCG') and
\
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] :
[]) + \
(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \
+ (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : [])
+ + \
['arm-cpu-features',
'numa-test',
'boot-serial-test',
diff --git a/tests/qtest/npcm8xx_pspi-test.c b/tests/qtest/npcm8xx_pspi-test.c
new file mode 100644 index 0000000000..13b8a8229c
--- /dev/null
+++ b/tests/qtest/npcm8xx_pspi-test.c
@@ -0,0 +1,118 @@
+/*
+ * QTests for the Nuvoton NPCM8XX PSPI Controller
+ *
+ * Copyright (c) 2025 Nuvoton Technology Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "qemu/module.h"
+
+/* Register offsets */
+#define DATA_OFFSET 0x00
+#define CTL_SPIEN 0x01
+#define CTL_OFFSET 0x02
+#define CTL_MOD 0x04
+
+typedef struct PSPI {
+ uint64_t base_addr;
+} PSPI;
+
+PSPI pspi_defs = {
+ .base_addr = 0xf0201000
+};
+
+static uint16_t pspi_read_data(QTestState *qts, const PSPI *pspi) {
+ return qtest_readw(qts, pspi->base_addr + DATA_OFFSET); }
+
+static void pspi_write_data(QTestState *qts, const PSPI *pspi, uint16_t
+value) {
+ qtest_writew(qts, pspi->base_addr + DATA_OFFSET, value); }
+
+static uint16_t pspi_read_ctl(QTestState *qts, const PSPI *pspi) {
+ return qtest_readw(qts, pspi->base_addr + CTL_OFFSET); }
+
+static void pspi_write_ctl(QTestState *qts, const PSPI *pspi, uint16_t
+value) {
+ qtest_writew(qts, pspi->base_addr + CTL_OFFSET, value); }
+
+/* Check PSPI can be reset to default value */ static void
+test_init(gconstpointer pspi_p) {
+ const PSPI *pspi = pspi_p;
+
+ QTestState *qts = qtest_init("-machine npcm845-evb");
+
+ /* Write CTL_SPIEN value to control register for enable PSPI module */
+ pspi_write_ctl(qts, pspi, CTL_SPIEN);
+ g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, CTL_SPIEN);
+
+ qtest_quit(qts);
+}
+
+/* Check PSPI can be r/w data register */ static void
+test_data(gconstpointer pspi_p) {
+ const PSPI *pspi = pspi_p;
+ uint16_t test = 0x1234;
+ uint16_t output;
+
+ QTestState *qts = qtest_init("-machine npcm845-evb");
+
+ /* Enable 16-bit data interface mode */
+ pspi_write_ctl(qts, pspi, CTL_MOD);
+ g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, CTL_MOD);
+
+ /* Write to data register */
+ pspi_write_data(qts, pspi, test);
+
+ /* Read from data register */
+ output = pspi_read_data(qts, pspi);
+ g_assert_cmphex(output, ==, test);
+
+ qtest_quit(qts);
+}
+
+/* Check PSPI can be r/w control register */ static void
+test_ctl(gconstpointer pspi_p) {
+ const PSPI *pspi = pspi_p;
+ uint8_t control = CTL_MOD;
+
+ QTestState *qts = qtest_init("-machine npcm845-evb");
+
+ /* Write CTL_MOD value to control register for 16-bit interface mode */
+ qtest_memwrite(qts, pspi->base_addr + CTL_OFFSET,
+ &control, sizeof(control));
+ g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, control);
+
+ qtest_quit(qts);
+}
+
+static void pspi_add_test(const char *name, const PSPI* wd,
+ GTestDataFunc fn)
+{
+ g_autofree char *full_name = g_strdup_printf("npcm8xx_pspi/%s", name);
+ qtest_add_data_func(full_name, wd, fn); }
+
+#define add_test(name, td) pspi_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ add_test(init, &pspi_defs);
+ add_test(ctl, &pspi_defs);
+ add_test(data, &pspi_defs);
+ return g_test_run();
+}
--
2.34.1
Reviewed-by: Tyrone Ting <kft...@nuvoton.com>
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