On Tue, Apr 01, 2025 at 09:01:56AM -0400, Xiaoyao Li wrote: > Date: Tue, 1 Apr 2025 09:01:56 -0400 > From: Xiaoyao Li <xiaoyao...@intel.com> > Subject: [PATCH v8 46/55] i386/tdx: Add supported CPUID bits related to TD > Attributes > X-Mailer: git-send-email 2.34.1 > > For TDX, some CPUID feature bit is configured via TD attributes. They > are not covered by tdx_caps.cpuid (which only contians the configurable > bits), but they are actually supported when the related attributre bit > is supported. > > Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com> > --- > target/i386/cpu.h | 4 +++ > target/i386/kvm/tdx.c | 59 +++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 63 insertions(+) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 115137279a1a..0e984ec42bb6 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -903,6 +903,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, > FeatureWord w); > #define CPUID_7_0_ECX_LA57 (1U << 16) > /* Read Processor ID */ > #define CPUID_7_0_ECX_RDPID (1U << 22) > +/* KeyLocker */ > +#define CPUID_7_0_ECX_KeyLocker (1U << 23) > /* Bus Lock Debug Exception */ > #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) > /* Cache Line Demote Instruction */ > @@ -963,6 +965,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, > FeatureWord w); > #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) > /* AVX512 BFloat16 Instruction */ > #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) > +/* Linear address space separation */ > +#define CPUID_7_1_EAX_LASS (1U << 6) > /* CMPCCXADD Instructions */ > #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) > /* Fast Zero REP MOVS */
The whole framework is very good for me. Since LASS/key locker are not yet supported, I think it's better to add the note (in the commit message or code) that they are helpful for future enabling. Of course, removing these two features would be best, as they cannot be covered by current testing. Regards, Zhao
