Tim Lee <timlee660...@gmail.com> writes:
> - Created qtest to check initialization of registers in PSPI Module
> - Implemented test into Build File
>
> Tested:
> ./build/tests/qtest/npcm8xx-pspi_test
>
> Signed-off-by: Tim Lee <timlee660...@gmail.com>
> ---
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 3 +
> tests/qtest/npcm8xx_pspi-test.c | 104 ++++++++++++++++++++++++++++++++
> 3 files changed, 108 insertions(+)
> create mode 100644 tests/qtest/npcm8xx_pspi-test.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d54b5578f8..0162f59bf7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -892,6 +892,7 @@ F: hw/sensor/adm1266.c
> F: include/hw/*/npcm*
> F: tests/qtest/npcm*
> F: tests/qtest/adm1266-test.c
> +F: tests/qtest/npcm8xx_pspi-test.c
> F: pc-bios/npcm7xx_bootrom.bin
> F: pc-bios/npcm8xx_bootrom.bin
> F: roms/vbootrom
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 3136d15e0f..88672a8b00 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -210,6 +210,8 @@ qtests_npcm7xx = \
> 'npcm7xx_watchdog_timer-test',
> 'npcm_gmac-test'] + \
> (slirp.found() ? ['npcm7xx_emc-test'] : [])
> +qtests_npcm8xx = \
> + ['npcm8xx_pspi-test']
> qtests_aspeed = \
> ['aspeed_hace-test',
> 'aspeed_smc-test',
> @@ -257,6 +259,7 @@ qtests_aarch64 = \
> (config_all_accel.has_key('CONFIG_TCG') and
> \
> config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] :
> []) + \
> (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) +
> \
> + (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \
> ['arm-cpu-features',
> 'numa-test',
> 'boot-serial-test',
> diff --git a/tests/qtest/npcm8xx_pspi-test.c b/tests/qtest/npcm8xx_pspi-test.c
> new file mode 100644
> index 0000000000..107bce681f
> --- /dev/null
> +++ b/tests/qtest/npcm8xx_pspi-test.c
> @@ -0,0 +1,104 @@
> +#include "qemu/osdep.h"
> +#include "libqtest.h"
> +#include "qemu/module.h"
> +
> +#define DATA_OFFSET 0x00
> +#define CTL_SPIEN 0x01
> +#define CTL_OFFSET 0x02
> +#define CTL_MOD 0x04
> +
> +typedef struct PSPI {
> + uint64_t base_addr;
> +} PSPI;
> +
> +PSPI pspi_defs = {
> + .base_addr = 0xf0201000
> +};
> +
> +static uint16_t pspi_read_data(QTestState *qts, const PSPI *pspi)
> +{
> + return qtest_readw(qts, pspi->base_addr + DATA_OFFSET);
> +}
> +
> +static void pspi_write_data(QTestState *qts, const PSPI *pspi, uint16_t
> value)
> +{
> + qtest_writew(qts, pspi->base_addr + DATA_OFFSET, value);
> +}
> +
> +static uint32_t pspi_read_ctl(QTestState *qts, const PSPI *pspi)
> +{
> + return qtest_readl(qts, pspi->base_addr + CTL_OFFSET);
> +}
> +
> +static void pspi_write_ctl(QTestState *qts, const PSPI *pspi, uint32_t value)
> +{
> + qtest_writel(qts, pspi->base_addr + CTL_OFFSET, value);
> +}
> +
> +/* Check PSPI can be reset to default value */
> +static void test_init(gconstpointer pspi_p)
> +{
> + const PSPI *pspi = pspi_p;
> +
> + QTestState *qts = qtest_init("-machine npcm845-evb");
> + pspi_write_ctl(qts, pspi, CTL_SPIEN);
> + g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, CTL_SPIEN);
> +
> + qtest_quit(qts);
> +}
> +
> +/* Check PSPI can be r/w data register */
> +static void test_data(gconstpointer pspi_p)
> +{
> + const PSPI *pspi = pspi_p;
> + uint16_t test = 0x1234;
> + uint16_t output;
> +
> + QTestState *qts = qtest_init("-machine npcm845-evb");
> +
> + /* Write to data register */
> + pspi_write_data(qts, pspi, test);
> + printf("Wrote 0x%x to data register\n", test);
> +
> + /* Read from data register */
> + output = pspi_read_data(qts, pspi);
> + printf("Read 0x%x from data register\n", output);
> +
> + qtest_quit(qts);
> +}
> +
> +/* Check PSPI can be r/w control register */
> +static void test_ctl(gconstpointer pspi_p)
> +{
> + const PSPI *pspi = pspi_p;
> + uint8_t control = CTL_MOD;
> +
> + QTestState *qts = qtest_init("-machine npcm845-evb");
> +
> + /* Write CTL_MOD value to control register for 16-bit interface mode */
> + qtest_memwrite(qts, pspi->base_addr + CTL_OFFSET,
> + &control, sizeof(control));
> + g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, control);
> + printf("Wrote CTL_MOD to control register\n");
> +
> + qtest_quit(qts);
> +}
> +
> +static void pspi_add_test(const char *name, const PSPI* wd,
> + GTestDataFunc fn)
> +{
> + g_autofree char *full_name = g_strdup_printf("npcm8xx_pspi/%s", name);
> + qtest_add_data_func(full_name, wd, fn);
> +}
> +
> +#define add_test(name, td) pspi_add_test(#name, td, test_##name)
> +
> +int main(int argc, char **argv)
> +{
> + g_test_init(&argc, &argv, NULL);
> +
> + add_test(init, &pspi_defs);
> + add_test(ctl, &pspi_defs);
> + add_test(data, &pspi_defs);
> + return g_test_run();
> +}
This fails on top of current master, please take a look:
$ QTEST_LOG=1 QTEST_QEMU_BINARY=./qemu-system-aarch64
./tests/qtest/npcm8xx_pspi-test
# random seed: R02S03f79fc48ba73b76c881f93f90b015e9
1..3
# Start of aarch64 tests
# Start of npcm8xx_pspi tests
# starting QEMU: exec ./qemu-system-aarch64 -qtest
unix:/tmp/qtest-32530.sock -qtest-log /dev/fd/2 -chardev
socket,path=/tmp/qtest-32530.qmp,id=char0 -mon
chardev=char0,mode=control -display none -audio none -machine
npcm845-evb -accel qtest
[I 0.000000] OPENED
[R +0.034918] endianness
[S +0.034944] OK little
{"QMP": {"version": {"qemu": {"micro": 50, "minor": 0, "major": 10},
"package": "v10.0.0-530-g88d6459dae"}, "capabilities": ["oob"]}}
{"execute": "qmp_capabilities"}
{"return": {}}
[R +0.037373] writel 0xf0201002 0x1
[S +0.037396] OK
[R +0.037417] readl 0xf0201002
[S +0.037426] OK 0x0000000000000000
**
ERROR:../tests/qtest/npcm8xx_pspi-test.c:45:test_init: assertion failed
(pspi_read_ctl(qts, pspi) == CTL_SPIEN): (0x00000000 == 0x00000001)
Bail out!
[I +0.037909] CLOSED
Aborted (core dumped)
